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/* Amstrad motherboard (How to tickle JavaCPC) */
The magic RAM in FPGA, getting two clock entry, is not as magical as I thinked : it does solve clock equations using the clock manager (DCM) and BUFG components (saying phase is freedom between input and output). If you want a set of clock synchronized do not add a BUFG in one of its wires. If you don't care about synchronize of two clocks, just add it and then it will help to solve finer and greater the clock manager equations of DCM while compiling.
==== Amstrad motherboard (How to tickle JavaCPC) FPGAmstrad_amstrad_motherboard schematic ==== Core This is the core part of FPGAmstrad, represents it does represent the motherboard schematic of Amstrad, it was made using original schematic of CPC, and aligned to JavaCPC source code.
JavaCPC is developed in Java, and Java is so cool (Java is better computer language ever, and VHDL is better FPGA language ever =P)
