Changes
/* FPGAmstrad_amstrad_video schematic */
The magic RAM in FPGA, getting two clock entries, is not as magical as I was thinking : in fact it does solve clock equations using the clock manager (DCM) and BUFG components (saying phase is freedom between input and output). If you want a set of clock synchronized do not add a BUFG in one of its wires. If you don't care about synchronize of two clocks, just add it and then it will help to solve finer and greater the clock manager equations of DCM while compiling.
If interested about stange strange clocks generated during last step of FPGA compile, do look after "time constraints file" and "timing closure".
==== FPGAmstrad_amstrad_motherboard schematic ====
