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Arnold V specs

1,290 bytes removed, 12:30, 15 August 2015
/* Common Features */
<font size="-2:>''Copyright Amstrad ©1990 plc''</font></center>
''Note: this is the original, unaltered document as circulated within Amstrad. It is not so much intended as a reference for Plus developers, since it contains certain errors. If you want to read a version that has been corrected at least at some points (thanks to Executioner), please go to [[Arnold_V_Specs_Revised]]''
 
''For more unaltered (read-only) txt/htm versions, see [[Original Arnold V Specs]]. The cpcwiki page that you are currently viewing seems to be based on the original RTF version, as indicated by the characterstically distorted printer pin-out table.''
==PRODUCT RANGE OVERVIEW==
The old CPC6128 keyboard is used, except that the colour scheme has been changed and the connecting cable exits in a different location.
NOTE: gerald (on the forums) has confirmed a fault in the ASIC when used with external memory expansions. If a page of an external memory expansion is activated in the range &4000-&7fff and the asic ram page is active and a write is done, the write will go to the asic ram AND to the external memory expansion. This bug is NOT seen when the extra 64KB inside the 6128Plus is active when the asic ram page is active. It is advised that you set the configuration to &7fc0 before accessing the asic ram.
===Amstrad 464 Plus===
===Interrupt service (Vectored interrupts)===
The ASIC can produce interrupts from four sources: the raster interrupt and the three sound generator "DMA" channels. The ASIC will always supply a vector which can be used by the CPU in interrupt modes 0 and 2 or ignored in interrupt mode 1.
The top 5 bits Bit D7 is set if the last interrupt acknowledge was for a raster interrupt. Bits D6-D4 of the vector will be supplied DCSR are set if interrupts from bit D7sound channels 0-D3 of 2 respectively are active. For compatibility with earlier models, the raster interrupt is reset either by a memory mapped CPU interrupt vector register (IVR) at address 6805h in the ASICacknowledge cycle, and the next two bits will determine the source or by writing a 1 to bit D4 of the interruptmode and ROM enable register. Bit D0 of the vector supplied is ignored The sound channel interrupts are cleared by writing a 1 to the Z80 relevant bit in interrupt mode 2, but may be used in interrupt mode 0 (???)the DCSR.
<pre>
D2 D1
0 0 DMA channel 2 interrupt vector
0 1 DMA channel 1 interrupt vector
1 0 DMA channel 0 interrupt vector
1 1 Raster interrupt vector
</pre>
 
The value written to bit D0 of the IVR controls whether DMA channel interrupts are automatically cleared, but has no effect on the vector itself (???). The contents of register 6805h are undefined at reset except that bit D0 will be set to 1. Software should always set up the IVR before placing the CPU in vectored interrupt mode.
 
The interrupts are prioritized in a fixed sequence. The raster interrupt has the highest priority, followed by DMA channels 2 down to 0 respectively. For compatibility with earlier models, the raster interrupt is reset either by a CPU interrupt acknowledge cycle, or by writing a 1 to bit D4 of the mode and ROM enable register. The sound channel interrupts are cleared by writing a 1 to the relevant bit in the DCSR. To simplify vectored interrupt systems, they may also be cleared automatically by a CPU interrupt acknowledge cycle. This feature is enabled by writing a 0 to bit D0 of IVR.
 
Bit D7 is set if the last interrupt acknowledge was for a raster interrupt. Bits D6-D4 of the DCSR are set if interrupts from sound channels 0-2 respectively are active. These bits can be ignored by software which uses vectored interrupts where the DMA interrupts are automatically cleared, or by software which does not use the DMA channel interrupt facility. If DMA channel interrupts are used and not automatically cleared, they must be acknowledged by writing a “1” to the relevant DCSR bit. If bit D0 of the IVR is set to 0 bits D4-D6 of the DCSR will be cleared before the CPU gets a chance to read them.
Thus interrupt service software in an environment where DMA interrupts are used must inspect these bits, giving highest priority to the raster interrupt, because this interrupt is always cleared automatically.
Failure to observe this requirement may result in raster interrupts being missed. Software which uses DMA interrupts from expansion cards must always use Z80 non-vectored interrupt mode be acknowledged by writing a "1, because " to the expansion bus does not support vectored interrupts.  To summarize, vectored software should place a valid vector (D0 = 0) into the IVR. The hardware will supply a different vector for each interrupt source, and all interrupts are acknowledge automaticallyrelevant DCSR bit.
Non vectored software must write a "1" to bit D0 of the IVR, or leave it in it's reset state. Interrupt service software must examine bit D7 of the DCSR first, followed by bits D4-D6 (in any sequence) to identify the interrupt source. DMA interrupts must be acknowledged by writing a "1" to the relevant DCSR bit.
===Enhanced ROM cartridge support===
0-7 0-7
High Bank: Logical page (DFxxh) Physical page 1
0-127 (not disc page) 1
The two ROM disable bits in the existing mode and ROM enable register disable the ROM as before, wherever it is mapped, as does the ROMDIS signal from the expansion bus.
The "write through" mechanism, whereby writes to an area which is currently mapped as ROM actually write to the underlying RAM, still functions, wherever the ROM is mapped. However the write through mechanism cannot be used to access the register page. Write through also does not operate to the RAM from the register page.
 
===Analogue paddle ports===
6802h 2 N W SSA Screen split secondary start address
6804h 1 Y W SSCR Soft scroll control register
6805h 1 N W IVR Interrupt Vector (Bit 0 set to 1 on reset)
6806h 6805h (unused)        ADDR SIZE POR TYPE MNEM USE
6808h 1 R ADC0 Analogue input channel 0
6C07h 1 (unused)
6C08h 2 N W SAR2 "DMA" channel 2 address pointer
6C0Ah 1 N W PPR2 "DMA" channel 2 pause prescaler 6C0Bh 4 (unused) 6C0Fh 1 Y R/W DCSR "DMA" control/status register</pre>
[[Category:CPC Plus]]
[[Category:Hardware]][[Category:CPC Internal Components]]
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