Changes
/* Common Features */
<font size="-2:>''Copyright Amstrad ©1990 plc''</font></center>
''Note: this is the original, unaltered document as circulated within Amstrad. It is not so much intended as a reference for Plus developers, since it contains certain errors. If you want to read a version that has been corrected at least at some points (thanks to Executioner), please go to [[Arnold_V_Specs_Revised]]''
''For more unaltered (read-only) txt/htm versions, see [[Original Arnold V Specs]]. The cpcwiki page that you are currently viewing seems to be based on the original RTF version, as indicated by the characterstically distorted printer pin-out table.''
==PRODUCT RANGE OVERVIEW==
The old CPC6128 keyboard is used, except that the colour scheme has been changed and the connecting cable exits in a different location.
NOTE: gerald (on the forums) has confirmed a fault in the ASIC when used with external memory expansions. If a page of an external memory expansion is activated in the range &4000-&7fff and the asic ram page is active and a write is done, the write will go to the asic ram AND to the external memory expansion. This bug is NOT seen when the extra 64KB inside the 6128Plus is active when the asic ram page is active. It is advised that you set the configuration to &7fc0 before accessing the asic ram.
===Amstrad 464 Plus===
The SAR must be loaded by the CPU with a physical RAM address between 0000h and FFFEh. This means that the most significant two bits select which pages 0 to 3 of the DRAM is used, and the remaining bits are the address relative to the page start. The DMA process is not affected by the RAM or ROM mapping registers, and will always fetch data from RAM and not ROM. Note that the least significant bit of the address is ignored, and the instructions are always fetched from word boundaries.
The pause prescaler counts N+1 scan lines (where N is the value written by the CPU), giving a minimum tick of 64us, and a maximum of 16.384ms. When set nonzero by a pause instruction, the pause counter for a particular channel is decremented every tick until it reaches zero. Therefore, if the PPR is set to a value N and a PAUSE M instruction is executed, the total delay time between the instruction before the PAUSE and that following the PAUSE will be M * (N+1) * 64us. Pauses of between 64us and 67s may thus be generated. If a DMA channel is executing a pause when the DMA channel is disabled or the SAR is changed, the pause counter will continue to decrement. It will not reset and when the DMA is again enabled and the command at the current SAR address will not be executed until the pause is complete. Changing the prescale value mid-pause will vary the length of the pause (eg. If the prescale is set to 0 and a PAUSE 10 is executed and has already decremented 5 times, changing the prescale to 1 will cause the pause to have a duration of 15 scan lines).
The ASIC arbitrates accesses to the parallel interface device between the "DMA" channels and the CPU, allowing only one to access it at a time. CPU accesses to the 8255 could be held off by means of wait states for up to 8 microseconds if the "DMA" channel is currently executing a LOAD instruction. After a LOAD is executed, the ASIC must put the PSG address register back as it was before. To achieve this the 8255 parallel peripheral interface and the 74LS145 decoder have been integrated into the ASIC.
The exact timing is based on 1us cycles as follows. After the leading edge from HSYN from the 6845 there is one dead cycle followed by an instruction fetch cycle for each channel which is active (i.e. enabled and not paused). The execute cycles then follow for each active channel. All instructions execute in one cycle, except that LOAD requires at least 8 cycles. An extra cycle is added to a LOAD if the CPU is accessing the 8255, or two extra cycles if the CPU access was itself a PSG register write.
The top 5 bits of ASIC can produce interrupts from four sources: the vector will be supplied from bit D7-D3 of a memory mapped raster interrupt vector register (IVR) at address 6805h in the ASIC, and the next two bits will determine the source of the interrupt. Bit D0 of the vector supplied is ignored by the Z80 in interrupt mode 2, but may be used in interrupt mode 0 (???)three sound generator "DMA" channels.
Thus interrupt service software in an environment where DMA interrupts are used must inspect these bits, giving highest priority to the raster interrupt, because this interrupt is always cleared automatically.
Failure to observe this requirement may result in raster interrupts being missed. Software which uses DMA interrupts from expansion cards must always use Z80 non-vectored interrupt mode be acknowledged by writing a "1, because " to the expansion bus does not support vectored interrupts. To summarize, vectored software should place a valid vector (D0 = 0) into the IVR. The hardware will supply a different vector for each interrupt source, and all interrupts are acknowledge automaticallyrelevant DCSR bit.
===Enhanced ROM cartridge support===
0-7 0-7
High Bank: Logical page (DFxxh) Physical page 1
0-127 (not disc page) 1
The two ROM disable bits in the existing mode and ROM enable register disable the ROM as before, wherever it is mapped, as does the ROMDIS signal from the expansion bus.
The "write through" mechanism, whereby writes to an area which is currently mapped as ROM actually write to the underlying RAM, still functions, wherever the ROM is mapped. However the write through mechanism cannot be used to access the register page. Write through also does not operate to the RAM from the register page.
===Analogue paddle ports===
6802h 2 N W SSA Screen split secondary start address
6804h 1 Y W SSCR Soft scroll control register
6808h 1 R ADC0 Analogue input channel 0
6C07h 1 (unused)
6C08h 2 N W SAR2 "DMA" channel 2 address pointer
6C0Ah 1 N W PPR2 "DMA" channel 2 pause prescaler 6C0Bh 4 (unused) 6C0Fh 1 Y R/W DCSR "DMA" control/status register</pre>
[[Category:CPC Plus]]
[[Category:Hardware]][[Category:CPC Internal Components]]
