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Last modified on 1 April 2025, at 03:42

Difference between revisions of "SYMBiFACE II:IDE registers"
 
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This is the documentation about the '''IDE registers''' of the [[SYMBiFACE II]] expansion card. For more information about IDE please check for general specifications in the internet ''(can anyone provide good links here?)''.
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The Symbiface 2 operates the ATA/IDE device in 16-bit data transfer mode. 16-bits of data is buffered at a time within the Symbiface 2 and read/written via the Data port I/O address 8 bits at a time. The device was designed when devices didn't support ATA CFA command set and 8-bit PIO data transfer so this is why it buffers 16-bit of data. (16-bits is the "native" data transfer of an ATA device).
 +
 
 +
The I/O ports operate in a "pass-through" like mode where the registers directly reflect those of the connected ATA device.
 +
 
 +
The [[X-Mass]] is a more modern ATA/IDE device which is compatible with the Symbiface 2 IDE registers and uses the same I/O ports.
 +
 
 +
This is the documentation about the '''IDE registers''' of the [[SYMBiFACE II]] expansion card.  
  
 
{|{{Prettytable|width: 700px; font-size: 2em;}}
 
{|{{Prettytable|width: 700px; font-size: 2em;}}
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|'''#FD08''' || Data Register || Data Register
 
|'''#FD08''' || Data Register || Data Register
 
|-
 
|-
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|'''#FD09''' || Error Register || ''(Write Precomp Reg.)''
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|'''#FD09''' || Error Register || Features Register/''(Write Precomp Reg.)''
 
|-
 
|-
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|'''#FD0A''' || Sector Count || Sector Count
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|'''#FD0A''' || Sector Count (0=256) || Sector Count (0=256)
 
|-
 
|-
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|'''#FD0B''' || Sector Number || Sector Number
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|'''#FD0B''' || Sector Number for CHS or LBA bits 0-7 || Sector Number for CHS or LBA bits 0-7
 
|-
 
|-
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|'''#FD0C''' || Cylinder Low || Cylinder Low
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|'''#FD0C''' || Cylinder Low for CHS or LBA bits 8-15 || Cylinder Low for CHS or LBA bits 8-15
 
|-
 
|-
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|'''#FD0D''' || Cylinder High || Cylinder High
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|'''#FD0D''' || Cylinder High for CHS or LBA bits 16-23 || Cylinder High for CHS or LBA bits 16-23
 
|-
 
|-
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|'''#FD0E''' || SDH Register || SDH Register
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|'''#FD0E''' || Device/Head Register (Bit 6=0 CHS, Bit 6=1 LBA) (Bit 4 = 0 Master, Bit 4 = 1 Slave) (Bits 3..0 Head for CHS or LBA bits 24-27) || Device/Head Register (Bit 6=0 CHS, Bit 6=1 LBA) (Bit 4 = 0 Master, Bit 4 = 1 Slave) (Bits 3..0 Head for CHS or LBA bits 24-27)
 
|-
 
|-
 
|'''#FD0F''' || Status Register || Command Register
 
|'''#FD0F''' || Status Register || Command Register
 
|}
 
|}
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 +
{| class="wikitable"
 +
|+ Mandatory ATA1 Commands
 +
! Command !! Code !! FR !! SC !! SN !! CY !! DH
 +
|-
 +
| Execute drive diagnostic || 90h || || || || || D*
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|-
 +
| Format track || 50h || * || y || y || y ||
 +
|-
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| Initialize drive parameters || 91h || || y || || || y
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|-
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| Read long (w/retry) || 22h || || y || y || y || y
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|-
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| Read long (w/o retry) || 23h || || y || y || y || y
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|-
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| Read sector(s) (w/retry) || 20h || || y || y || y || y
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|-
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| Read sector(s) (w/o retry) || 21h || || y || y || y || y
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|-
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| Read verify sector(s) (w/retry) || 40h || || y || y || y || y
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|-
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| Read verify sector(s) (w/o retry) || 41h || || y || y || y || y
 +
|-
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| Recalibrate || 1xh || || || || || D
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|-
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| Seek || 7xh || || || y || y || y
 +
|-
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| Write long (w/retry) || 32h || * || y || y || y || y
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|-
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| Write long (w/o retry) || 33h || * || y || y || y || y
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|-
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| Write sector(s) (w/retry) || 30h || * || y || y || y || y
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|-
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| Write sector(s) (w/o retry) || 31h || * || y || y || y || y
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|}
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'''Legend:'''
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* '''FR:''' Features register used
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* '''SC:''' Sector count register used
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* '''SN:''' Sector number register used
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* '''CY:''' Cylinder registers used
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* '''DH:''' Drive/head register used
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** '''y:''' The register contains a valid parameter for this command. For DH, 'y' means both drive and head parameters are used.
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** '''D:''' Only the drive parameter is valid (head parameter ignored).
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** '''D*:''' Addressed to drive 0 but both drives execute it.
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** '''*:''' Maintained for compatibility.
  
 
== See also ==
 
== See also ==
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* [[SYMBiFACE II:IDE routines|Low level IDE routines]]
 
* [[SYMBiFACE II:IDE routines|Low level IDE routines]]
 
* [[Programming:SYMBiFACE_II|SYMBiFACE II documentations]]
 
* [[Programming:SYMBiFACE_II|SYMBiFACE II documentations]]
−
* [[http://www.t13.org/documents/uploadeddocuments/docs2006/d1699r3f-ata8-acs.pdf|ATA/IDE specification]]
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* [https://hddguru.com/documentation/ Official ATA1 (1994) to ATA8 (2006) specifications]
 
[[Category:Programming]]
 
[[Category:Programming]]

Latest revision as of 03:42, 1 April 2025

The Symbiface 2 operates the ATA/IDE device in 16-bit data transfer mode. 16-bits of data is buffered at a time within the Symbiface 2 and read/written via the Data port I/O address 8 bits at a time. The device was designed when devices didn't support ATA CFA command set and 8-bit PIO data transfer so this is why it buffers 16-bit of data. (16-bits is the "native" data transfer of an ATA device).

The I/O ports operate in a "pass-through" like mode where the registers directly reflect those of the connected ATA device.

The X-Mass is a more modern ATA/IDE device which is compatible with the Symbiface 2 IDE registers and uses the same I/O ports.

This is the documentation about the IDE registers of the SYMBiFACE II expansion card.

Port Read Write
#FD06 Alternate Status Digital Output
#FD07 Drive Address (Not Used)
#FD08 Data Register Data Register
#FD09 Error Register Features Register/(Write Precomp Reg.)
#FD0A Sector Count (0=256) Sector Count (0=256)
#FD0B Sector Number for CHS or LBA bits 0-7 Sector Number for CHS or LBA bits 0-7
#FD0C Cylinder Low for CHS or LBA bits 8-15 Cylinder Low for CHS or LBA bits 8-15
#FD0D Cylinder High for CHS or LBA bits 16-23 Cylinder High for CHS or LBA bits 16-23
#FD0E Device/Head Register (Bit 6=0 CHS, Bit 6=1 LBA) (Bit 4 = 0 Master, Bit 4 = 1 Slave) (Bits 3..0 Head for CHS or LBA bits 24-27) Device/Head Register (Bit 6=0 CHS, Bit 6=1 LBA) (Bit 4 = 0 Master, Bit 4 = 1 Slave) (Bits 3..0 Head for CHS or LBA bits 24-27)
#FD0F Status Register Command Register
Mandatory ATA1 Commands
Command Code FR SC SN CY DH
Execute drive diagnostic 90h D*
Format track 50h * y y y
Initialize drive parameters 91h y y
Read long (w/retry) 22h y y y y
Read long (w/o retry) 23h y y y y
Read sector(s) (w/retry) 20h y y y y
Read sector(s) (w/o retry) 21h y y y y
Read verify sector(s) (w/retry) 40h y y y y
Read verify sector(s) (w/o retry) 41h y y y y
Recalibrate 1xh D
Seek 7xh y y y
Write long (w/retry) 32h * y y y y
Write long (w/o retry) 33h * y y y y
Write sector(s) (w/retry) 30h * y y y y
Write sector(s) (w/o retry) 31h * y y y y

Legend:

  • FR: Features register used
  • SC: Sector count register used
  • SN: Sector number register used
  • CY: Cylinder registers used
  • DH: Drive/head register used
    • y: The register contains a valid parameter for this command. For DH, 'y' means both drive and head parameters are used.
    • D: Only the drive parameter is valid (head parameter ignored).
    • D*: Addressed to drive 0 but both drives execute it.
    • *: Maintained for compatibility.

See also