Changes
/* Interrupt service (Vectored interrupts) */
</pre>
The value written to bit D0 of the IVR controls whether DMA channel interrupts are automatically cleared. The contents of register 6805h are undefined at reset except that bit D0 will be set to 1. Software should therefore always set up the IVR before placing the CPU in vectored interrupt modeso that the top bit 5 bits are defined.
The interrupts are prioritized in a fixed sequence. The raster interrupt has the highest priority, followed by DMA channels 2 down to 0 respectively. For compatibility with earlier models, the raster interrupt is reset either by a CPU interrupt acknowledge cycle, or by writing a 1 to bit D4 of the mode and ROM enable register. The sound channel interrupts are cleared by writing a 1 to the relevant bit in the DCSR. To simplify vectored interrupt systems, they may also be cleared automatically by a CPU interrupt acknowledge cycle. This feature is enabled by writing a 0 to bit D0 of IVR.
Bit D7 is set if the last interrupt acknowledge was for a raster interrupt. Bits D6-D4 of the DCSR are set if interrupts from sound channels 0-2 respectively are active. These bits can be ignored by software which uses vectored interrupts where the DMA interrupts are automatically cleared, or by software which does not use the DMA channel interrupt facility. If DMA channel interrupts are used and not automatically cleared, they must be acknowledged by writing a “1” to the relevant DCSR bit. If bit D0 of the IVR is set to 0 bits D4-D6 of the DCSR will be cleared before the CPU gets a chance to read them.
If IVR bit 0 is set to 1, a DMA channel is interrupting and is not acknowledged then it will continue to interrupt until it is acknowledged.
Thus interrupt service software in an environment where DMA interrupts are used must inspect these bits, giving highest priority to the raster interrupt, because this interrupt is always cleared automatically.Failure to observe this requirement may result in raster interrupts being missed.
Software which uses interrupts from expansion cards must always use Z80 non-vectored interrupt mode 1, because the expansion bus does not support vectored interrupts. (The ASIC doesn't recognise the RETI command sequence and the expansion bus doesn't support IEO or IEI which is used to control IM2 interrupt priority.)
To summarize, vectored software should place a valid vector (D0 = 0) into the IVR. The hardware will supply a different vector for each interrupt source, and all interrupts are acknowledge automatically.
Non vectored software must write a "1" to bit D0 of the IVR, or leave it in it's reset state. Interrupt service software must examine bit D7 of the DCSR first, followed by bits D4-D6 (in any sequence) to identify the interrupt source. DMA interrupts must be acknowledged by writing a "1" to the relevant DCSR bit.
NOTE: Vectored interrupts are bugged. When IM 2 Following discussions on cpcwiki involving roudoudou, Longshot, gerald, arnoldemu and dragon, it has been found that if the instruction which is setbeing interrupted is located in a memory region where A13=1 (i.e. &2000-&3fff, &6000-&7fff, &a000-&cfff, &e000-&ffff) then the vector for bug will not occur. When the raster interrupt changes instruction is in a memory region where A13=0 then the vector will be seen to change between 6 and 4. It This is 6 when related to if the instruction that was interrupted doesn't perform CPU is performing a memory read or /write, 4 if it does. Multi-byte opcodes are generally an opcode read The bug is independent of the value of I register, followed by a memory read for the remaining opcode bytes. So this also qualifies. This is true regardless location of whether DMA is activethe interrupt service routine, or PRI interrupts are used or notthe location of the vector table which has the interrupt service routine addresses.
Advice, if you use IM2, set either point all vector functions interrupt vectors to the same function. Do not use auto-clear interrupt handler and handle it all in one function as if you had used IM manually acknowledge the dma interrupts OR locate your code where A13=1.
===Enhanced ROM cartridge support===
