Externally, the processor uses a 16‑bit data bus, so memory accesses occur in 16‑bit (word) units, though it supports byte accesses via data strobes. The address bus is 24 bits wide; while internal address computations occur using 32‑bit arithmetic, only the lower 24 bits are available on the physical pins. This design yields a flat memory model with a maximum addressable space of 16 MB without the complications of segmentation, simplifying both operating system design and application programming.
== Register Structure and Condition Codes ==
The 68000’s register file is one of its most celebrated features. It provides:
* Data Registers (D0–D7): These are 32 bits wide and are used for general-purpose arithmetic and logical operations. However, when operating on byte or word data, only the lower 8 or 16 bits are affected.
* Address Registers (A0–A7): Also 32 bits wide, these registers are used for pointer operations and addressing modes. A7 doubles as the stack pointer (SP), and separate supervisor (SSP) and user (USP) stacks are supported in privileged modes.
* Status Register (SR): This 16‑bit register comprises an 8‑bit system byte (accessible only in supervisor mode) and an 8‑bit user byte known as the condition code register (CCR). The CCR contains the standard flags—zero (Z), carry (C), overflow (V), negative (N), and extend (X). Notably, the extend bit is used in multi‑precision arithmetic to propagate carries between successive 16‑bit operations, which is critical given that the ALU is only 16 bits wide.
== Instruction Set and Addressing Modes ==