| add ixy,qq || DD/FD 00qq1001 || 4 || 15 (4,4,4,3) || - || - || + || + || + || - || 0 || + || ixy += qq
|-
| adc hl,qq || 11101101 ED 01qq1010 || 4 || 15 (4,4,4,3) || + || + || + || + || + || V || 0 || + || hl += qq + cf ||Add with Carry
|-
| sbc hl,qq || 11101101 ED 01qq0010 || 4 || 15 (4,4,4,3) || + || + || + || + || + || V || 1 || + || hl -= qq + cf ||Subtract with Carry
|}
|| Decimal Adjust Accumulator
|-
| rrd || 11101101 ED 01100111 || 5 || 18 (4,4,3,4,3) || + || + || + || 0 || + || P || 0 || - || tmp := (hl), (hl) := [tmp >> 4] + [[a and 0x0f] << 4],
a := [a and 0xf0] + [tmp and 0x0f] => flags
|| Rotate Right Decimal
|-
| rld || 11101101 ED 01101111 || 5 || 18 (4,4,3,4,3) || + || + || + || 0 || + || P || 0 || - || tmp := [(hl) << 4] + [a and 0x0f], (hl) := tmp,
a := [a and 0xf0] + [tmp >> 8] => flags
|| Rotate Left Decimal
| rra || 00011111 || 1 || 4 (4) || - || - || + || 0 || + || - || 0 || X || ocf := cf, cf := a.0, a := [a >> 1] + [ocf << 7]
|-
| rl r || 11001011 CB 00010rrr || 2 || 8 (4,4) || + || + || + || 0 || + || P || 0 || X || ocf := cf, cf := r.7, r := [r << 1] + ocf ||rowspan=4|Rotate Left
|-
| rl (hl) || 11001011 CB 00010110 || 4 || 15 (4,4,4,3) || + || + || + || 0 || + || P || 0 || X || ocf := cf, cf := (hl).7, (hl) := [(hl) << 1] + ocf
|-
| rl (ixy+d) || DD/FD 11001011 CB dddddddd 00010110 || 7 || 23 (4,4,3,5,4,3) || + || + || + || 0 || + || P || 0 || X || ocf := cf, cf := (ixy+d).7, (ixy+d) := [(ixy+d) << 1] + ocf
|-
| rl (ixy+d)->r || DD/FD 11001011 CB dddddddd 00010rrr || 7 || 23 (4,4,3,5,4,3) || + || + || + || 0 || + || P || 0 || X || ocf := cf, cf := (ixy+d).7, (ixy+d) := r := [(ixy+d) << 1] + ocf
|-
| rlc r || 11001011 CB 00000rrr || 2 || 8 (4,4) || + || + || + || 0 || + || P || 0 || X || cf := r.7, r := [r << 1] + cf ||rowspan=4|Rotate Left Carry
|-
| rlc (hl) || 11001011 CB 00000110 || 4 || 15 (4,4,4,3) || + || + || + || 0 || + || P || 0 || X || cf := (hl).7, (hl) := [(hl) << 1] + cf
|-
| rlc (ixy+d) || DD/FD 11001011 CB dddddddd 00000110 || 7 || 23 (4,4,3,5,4,3) || + || + || + || 0 || + || P || 0 || X || cf := (ixy+d).7, (ixy+d) := [(ixy+d) << 1] + cf
|-
| rlc (ixy+d)->r || DD/FD 11001011 CB dddddddd 00000rrr || 7 || 23 (4,4,3,5,4,3) || + || + || + || 0 || + || P || 0 || X || cf := (ixy+d).7, (ixy+d) := r := [(ixy+d) << 1] + cf
|-
| rr r || 11001011 CB 00011rrr || 2 || 8 (4,4) || + || + || + || 0 || + || P || 0 || X || ocf := cf, cf := r.0, r := [r >> 1] + [ocf << 7] ||rowspan=4|Rotate Right
|-
| rr (hl) || 11001011 CB 00011110 || 4 || 15 (4,4,4,3) || + || + || + || 0 || + || P || 0 || X || ocf := cf, cf := (hl).0, (hl) := [(hl) >> 1] + [ocf << 7]
|-
| rr (ixy+d) || DD/FD 11001011 CB dddddddd 00011110 || 7 || 23 (4,4,3,5,4,3) || + || + || + || 0 || + || P || 0 || X || ocf := cf, cf := (ixy+d).0, (ixy+d) := [(ixy+d) >> 1] + [ocf << 7]
|-
| rr (ixy+d)->r || DD/FD 11001011 CB dddddddd 00011rrr || 7 || 23 (4,4,3,5,4,3) || + || + || + || 0 || + || P || 0 || X || ocf := cf, cf := (ixy+d).0, (ixy+d) := r := [(ixy+d) >> 1] + [ocf << 7]
|-
| rrc r || 11001011 CB 00001rrr || 2 || 8 (4,4) || + || + || + || 0 || + || P || 0 || X || cf := r.0, r := [r >> 1] + [cf << 7] ||rowspan=4|Rotate Right Carry
|-
| rrc (hl) || 11001011 CB 00001110 || 4 || 15 (4,4,4,3) || + || + || + || 0 || + || P || 0 || X || cf := (hl).0, (hl) := [(hl) >> 1] + [cf << 7]
|-
| rrc (ixy+d) || DD/FD 11001011 CB dddddddd 00001110 || 7 || 23 (4,4,3,5,4,3) || + || + || + || 0 || + || P || 0 || X || cf := (ixy+d).0, (ixy+d) := [(ixy+d) >> 1] + [cf << 7]
|-
| rrc (ixy+d)->r || DD/FD 11001011 CB dddddddd 00001rrr || 7 || 23 (4,4,3,5,4,3) || + || + || + || 0 || + || P || 0 || X || cf := (ixy+d).0, (ixy+d) := r := [(ixy+d) >> 1] + [cf << 7]
|-
| sla r || 11001011 CB 00100rrr || 2 || 8 (4,4) || + || + || + || 0 || + || P || 0 || X || cf := r.7, r := r << 1 ||rowspan=4|Shift Left Arithmetic
|-
| sla (hl) || 11001011 CB 00100110 || 4 || 15 (4,4,4,3) || + || + || + || 0 || + || P || 0 || X || cf := (hl).7, (hl) := (hl) << 1
|-
| sla (ixy+d) || DD/FD 11001011 CB dddddddd 00100110 || 7 || 23 (4,4,3,5,4,3) || + || + || + || 0 || + || P || 0 || X || cf := (ixy+d).7, (ixy+d) := (ixy+d) << 1
|-
| sla (ixy+d)->r || DD/FD 11001011 CB dddddddd 00100rrr || 7 || 23 (4,4,3,5,4,3) || + || + || + || 0 || + || P || 0 || X || cf := (ixy+d).7, (ixy+d) := r := (ixy+d) << 1
|-
| sra r || 11001011 CB 00101rrr || 2 || 8 (4,4) || + || + || + || 0 || + || P || 0 || X || cf := r.0, r := r >> 1, r.7 := r.6 ||rowspan=4|Shift Right Arithmetic
|-
| sra (hl) || 11001011 CB 00101110 || 4 || 15 (4,4,4,3) || + || + || + || 0 || + || P || 0 || X || cf := (hl).0, (hl) := (hl) >> 1, (hl).7 := (hl).6
|-
| sra (ixy+d) || DD/FD 11001011 CB dddddddd 00101110 || 7 || 23 (4,4,3,5,4,3) || + || + || + || 0 || + || P || 0 || X || cf := (ixy+d).0, (ixy+d) := (ixy+d) >> 1, (ixy+d).7 := (ixy+d).6
|-
| sra (ixy+d)->r || DD/FD 11001011 CB dddddddd 00101rrr || 7 || 23 (4,4,3,5,4,3) || + || + || + || 0 || + || P || 0 || X || cf := (ixy+d).0, tmp := (ixy+d) >> 1, tmp.7 := tmp.6, (ixy+d) := r := tmp
|-
| sll r || 11001011 CB 00110rrr || 2 || 8 (4,4) || + || + || + || 0 || + || P || 0 || X || cf := r.7, r := [r << 1] + 1 ||rowspan=4|Shift Left Logical
|-
| sll (hl) || 11001011 CB 00110110 || 4 || 15 (4,4,4,3) || + || + || + || 0 || + || P || 0 || X || cf := (hl).7, (hl) := [(hl) << 1] + 1
|-
| sll (ixy+d) || DD/FD 11001011 CB dddddddd 00110110 || 7 || 23 (4,4,3,5,4,3) || + || + || + || 0 || + || P || 0 || X || cf := (ixy+d).7, (ixy+d) := [(ixy+d) << 1] + 1
|-
| sll (ixy+d)->r || DD/FD 11001011 CB dddddddd 00110rrr || 7 || 23 (4,4,3,5,4,3) || + || + || + || 0 || + || P || 0 || X || cf := (ixy+d).7, (ixy+d) := r := [(ixy+d) << 1] + 1
|-
| srl r || 11001011 CB 00111rrr || 2 || 8 (4,4) || 0 || + || + || 0 || + || P || 0 || X || cf := r.0, r := r >> 1 ||rowspan=4|Shift Right Logical
|-
| srl (hl) || 11001011 CB 00111110 || 4 || 15 (4,4,3) || 0 || + || + || 0 || + || P || 0 || X || cf := (hl).0, (hl) := (hl) >> 1
|-
| srl (ixy+d) || DD/FD 11001011 CB dddddddd 00111110 || 7 || 23 (4,4,3,5,4,3) || 0 || + || + || 0 || + || P || 0 || X || cf := (ixy+d).0, (ixy+d) := (ixy+d) >> 1
|-
| srl (ixy+d)->r || DD/FD 11001011 CB dddddddd 00111rrr || 7 || 23 (4,4,3,5,4,3) || 0 || + || + || 0 || + || P || 0 || X || cf := (ixy+d).0, (ixy+d) := r := (ixy+d) >> 1
|}
! Instruction !! Opcode !! NOPs !! Cycles !! S !! Z !! 5 !! H !! 3 !! P !! N !! C !! Effect !! Description
|-
| bit b,r || 11001011 CB 01bbbrrr || 2 || 8 (4,4) || + || + || + || 1 || + || P || 0 || - || tmp := r and [1 << b] ||rowspan=3|Test Bit
|-
| bit b,(hl) || 11001011 CB 01bbb110 || 3 || 12 (4,4,4) || + || + || X || 1 || X || P || 0 || - || tmp := (hl) and [1 << b],
f5 := wz.13, f3 := wz.11
|-
| bit b,(ixy+d) || DD/FD 11001011 CB dddddddd 01bbb*** || 6 || 20 (4,4,3,5,4) || + || + || X || 1 || X || P || 0 || - || tmp := (ixy+d) and [1 << b],
f5 := [ixy+d].13, f3 := [ixy+d].11
|-
| res b,r || 11001011 CB 10bbbrrr || 2 || 8 (4,4) || - || - || - || - || - || - || - || - || r := r and ~[1 << b] ||rowspan=4|Reset Bit
|-
| res b,(hl) || 11001011 CB 10bbb110 || 4 || 15 (4,4,4,3) || - || - || - || - || - || - || - || - || (hl) := (hl) and ~[1 << b]
|-
| res b,(ixy+d) || DD/FD 11001011 CB dddddddd 10bbb110 || 7 || 23 (4,4,3,5,4,3) || - || - || - || - || - || - || - || - || (ixy+d) := (ixy+d) and ~[1 << b]
|-
| res b,(ixy+d)->r || DD/FD 11001011 CB dddddddd 10bbbrrr || 7 || 23 (4,4,3,5,4,3) || - || - || - || - || - || - || - || - || (ixy+d) := r := (ixy+d) and ~[1 << b]
|-
| set b,r || 11001011 CB 11bbbrrr || 2 || 8 (4,4) || - || - || - || - || - || - || - || - || r := r or [1 << b] ||rowspan=4|Set Bit
|-
| set b,(hl) || 11001011 CB 11bbb110 || 4 || 15 (4,4,4,3) || - || - || - || - || - || - || - || - || (hl) := (hl) or [1 << b]
|-
| set b,(ixy+d) || DD/FD 11001011 CB dddddddd 11bbb110 || 7 || 23 (4,4,3,5,4,3) || - || - || - || - || - || - || - || - || (ixy+d) := (ixy+d) or [1 << b]
|-
| set b,(ixy+d)->r || DD/FD 11001011 CB dddddddd 11bbbrrr || 7 || 23 (4,4,3,5,4,3) || - || - || - || - || - || - || - || - || (ixy+d) := r := (ixy+d) or [1 << b]
|-
| cpl || 00101111 || 1 || 4 (4) || - || - || + || 1 || + || - || 1 || - || a := ~a || Complement
|-
| neg || 11101101 ED 01***100 || 2 || 8 (4,4) || + || + || + || + || + || V || 1 || + || a := 0 - a || Negate
|}
! Instruction !! Opcode !! NOPs !! Cycles !! S !! Z !! 5 !! H !! 3 !! P !! N !! C !! Effect !! Description
|-
| ldi || 11101101 ED 10100000 || 5 || 16 (4,4,3,5) || - || - || X || 0 || X || C || 0 || - || tmp := (hl), (de) := tmp, de += 1, hl += 1,
bc -= 1, f5 := [tmp + a].1, f3 := [tmp + a].3
|| Load and Increment
|-
| ldd || 11101101 ED 10101000 || 5 || 16 (4,4,3,5) || - || - || X || 0 || X || C || 0 || - || tmp := (hl), (de) := tmp, de -= 1, hl -= 1,
bc -= 1, f5 := [tmp + a].1, f3 := [tmp + a].3
|| Load and Decrement
|-
| ldir || 11101101 ED 10110000 || 6/5 || 21/16 (4,4,3,5,5)/(4,4,3,5) || - || - || X || 0 || X || C || 0 || - || ldi, if bc <> 0 then pc -= 2 || Load and Increment, Repeat
|-
| lddr || 11101101 ED 10111000 || 6/5 || 21/16 (4,4,3,5,5)/(4,4,3,5) || - || - || X || 0 || X || C || 0 || - || ldd, if bc <> 0 then pc -= 2 || Load and Decrement, Repeat
|-
| cpi || 11101101 ED 10100001 || 4 || 16 (4,4,3,5)|| + || + || X || + || X || C || 1 || - || tmp := a - (hl) => flags, bc -= 1, hl += 1,
f5 := [tmp - hf].1, f3 = [tmp - hf].3
|| Compare and Increment
|-
| cpd || 11101101 ED 10101001 || 4 || 16 (4,4,3,5) || + || + || X || + || X || C || 1 || - || tmp := a - (hl) => flags, bc -= 1, hl -= 1,
f5 := [tmp - hf].1, f3 = [tmp - hf].3
|| Compare and Decrement
|-
| cpir || 11101101 ED 10110001 || 6/4 || 21/16 (4,4,3,5,5)/(4,4,3,5) || + || + || X || + || X || C || 1 || - || cpi, if bc <> 0 and nz then pc -= 2 || Compare and Increment, Repeat
|-
| cpdr || 11101101 ED 10111001 || 6/4 || 21/16 (4,4,3,5,5)/(4,4,3,5) || + || + || X || + || X || C || 1 || - || cpd, if bc <> 0 and nz then pc -= 2 || Compare and Decrement, Repeat
|-
| ini || 11101101 ED 10100010 || 5 || 16 (4,5,4,3) || + || + || + || X || + || X || X || X || tmp := ((c)), (hl) := tmp, hl += 1,
b -= 1 => flags, nf := tmp.7,
|| I/O Input and Increment
|-
| ind || 11101101 ED 10101010 || 5 || 16 (4,5,4,3) || + || + || + || X || + || X || X || X || tmp := ((c)), (hl) := tmp, hl -= 1,
b -= 1 => flags, nf := tmp.7,
|| I/O Input and Decrement
|-
| inir || 11101101 ED 10110010 || 6/5 || 21/16 (4,5,4,3,5)/(4,5,4,3) || + || + || + || X || + || X || X || X || ini, if b <> 0 then pc -= 2 || I/O Input and Increment, Repeat
|-
| indr || 11101101 ED 10111010 || 6/5 || 21/16 (4,5,4,3,5)/(4,5,4,3) || + || + || + || X || + || X || X || X || ind, if b <> 0 then pc -= 2 || I/O Input and Decrement, Repeat
|-
| outi || 11101101 ED 10100011 || 5 || 16 (4,5,3,4) || + || + || + || X || + || X || X || X || tmp := (hl), ((c)) := tmp, hl += 1,
b -= 1 => flags, nf := tmp.7, tmp2 = tmp + l,
|| I/O Output and Increment
|-
| outd || 11101101 ED 10101011 || 5 || 16 (4,5,3,4) || + || + || + || X || + || X || X || X || tmp := (hl), ((c)) := tmp, hl -= 1,
b -= 1 => flags, nf := tmp.7, tmp2 = tmp + l,
|| I/O Output and Decrement
|-
| otir || 11101101 ED 10110011 || 6/5 || 21/16 (4,5,3,4,5)/(4,5,3,4) || + || + || + || X || + || X || X || X || outi, if b <> 0 then pc -= 2 || I/O Output and Increment, Repeat
|-
| otdr || 11101101 ED 10111011 || 6/5 || 21/16 (4,5,3,4,5)/(4,5,3,4) || + || + || + || X || + || X || X || X || outd, if b <> 0 then pc -= 2 || I/O Output and Decrement, Repeat
|}
| in a,(n) || 11011011 nnnnnnnn || 3 || 11 (4,3,4) || - || - || - || - || - || - || - || - || a := ((n)) ||rowspan=3|I/O Input
|-
| in r,(c) || 11101101 ED 01rrr000 || 4 || 12 (4,4,4) || + || + || + || 0 || + || P || 0 || - || r := ((c))
|-
| in f,(c) || 11101101 ED 01110000 || 4 || 12 (4,4,4) || + || + || + || 0 || + || P || 0 || - || tmp := ((c))
|-
| out (n),a || 11010011 nnnnnnnn || 3 || 11 (4,3,4) || - || - || - || - || - || - || - || - || ((n)) := a ||rowspan=3| I/O Output
|-
| out (c),r || 11101101 ED 01rrr001 || 4 || 12 (4,4,4) || - || - || - || - || - || - || - || - || ((c)) := r
|-
| out (c),0 || 11101101 ED 01110001 || 4 || 12 (4,4,4) || - || - || - || - || - || - || - || - || ((c)) := 0 (255 on CMOS CPU)
|}
| ret cc || 11ccc000 || 4/2 || 11/5 (5,3,3)/(5)|| - || - || - || - || - || - || - || - || if cc then pc := (sp), sp += 2 || Conditional return
|-
| reti || 11101101 ED 01001101 || 4 || 14 (4,4,3,3) || - || - || - || - || - || - || - || - || pc := (sp), sp += 2, iff1 := iff2 || Return from interrupt
|-
| retn || 11101101 ED 01***101 || 4 || 14 (4,4,3,3) || - || - || - || - || - || - || - || - || pc := (sp), sp += 2, iff1 := iff2 || Return from NMI
|-
| rst t || 11ttt111 || 4 || 11 (5,3,3) || - || - || - || - || - || - || - || - || sp -= 2, (sp) := pc, pc := t || Restart
| ei || 11111011 || 1 || 4 (4) || - || - || - || - || - || - || - || - || iff1 := 1, iff2 := 1 after the next instruction || Enable Interrupts
|-
| im m || 11101101 ED 01mmm110 || 2 || 8 (4,4) || - || - || - || - || - || - || - || - || im := m ||Set Interrupt Mode
mmm: 000=0, 001=0, 010=1, 011=2, 100=0, 101=0, 110=1, 111=2
|-
| ld i,a || 11101101 ED 01000111 || 3 || 9 (4,5) || - || - || - || - || - || - || - || - || i := a || rowspan=4|CPU State Load
|-
| ld r,a || 11101101 ED 01001111 || 3 || 9 (4,5) || - || - || - || - || - || - || - || - || r := a
|-
| ld a,i || 11101101 ED 01010111 || 3 || 9 (4,5) || + || + || + || 0 || + || X || 0 || - || a := i, pf := iff2
|-
| ld a,r || 11101101 ED 01011111 || 3 || 9 (4,5) || + || + || + || 0 || + || X || 0 || - || a := r, pf := iff2
|}
| ld ixy,nn || DD/FD 00100001 lolololo hihihihi || 4 || 14 (4,4,3,3) || - || - || - || - || - || - || - || - || ixy := nn
|-
| ld (nn),dd || 11101101 ED 01qq0011 lolololo hihihihi || 6 || 20 (4,4,3,3,3,3) || - || - || - || - || - || - || - || - || (nn) := dd
|-
| ld dd,(nn) || 11101101 ED 01qq1011 lolololo hihihihi || 6 || 20 (4,4,3,3,3,3) || - || - || - || - || - || - || - || - || dd := (nn)
|-
| ld (nn),hl || 00100010 lolololo hihihihi || 5 || 16 (4,3,3,3,3) || - || - || - || - || - || - || - || - || (nn) := hl