Changes

A new 8 bit memory mapped register (PRI) has been added within the ASIC at address 6800h, which is cleared at power up. If zero, the normal raster interrupt mechanism (CPC style interrupts) functions as before. Otherwise, an interrupt occurs on the leading edge of the HSYNC.. The PRI can be reprogrammed as required to produce multiple interrupts per frame. The raster interrupt occurs immediately is triggered on the leading trailing edge of the HSYNC sent to the monitor and the combined logic of HSYNC active AND raster matched. The raster line is calculated as Vertical Character Count * 8 or Vertical Line Count. If the HSYNC position and duration programmed in the CRTC causes the HSYNC to still be active on the first horizontal character of a new scan line, the interrupt may occur twice for the programmed scan line (once at the start of the line, then again when the HSYNC starts at the end of the same line). See section 2.7 below for general information on interrupts.