Changes
/* Locking of enhanced features */
<pre>FF,77,B3,51,A8,D4,62,39,9C,46,2B,15,8A,CD,EE</pre>
The lock will then be picked. If it required to lock it again, the same sequence must be followed but without the terminating "EE".
When the lock is "locked", the secondary ROM mapping register does not exist (see Section 2.6). It is therefore impossible to select (or to deselect) the memory mapped register page.
The unlocking sequence has found to be:
<pre><not zero> <zero>
&ff,&77,&b3,&51,&a8,&d4,&62,&39,&9c,&46,&2b,&15,&8a,&cd
<any value></pre>
The locking sequence has found to be:
<not zero> <zero>
&ff,&77,&b3,&51,&a8,&d4,&62,&39,&9c,&46,&2b,&15,&8a
<any value - but not &cd>
Notes:
* asic is locked after hard reset (e.g. reset switch) or power on/off
* asic lock/unlock sequence enables/blocks the I/O port for making the ASIC registers visible in the z80 address space.
* asic lock remains in it's current state until the sequence completes
* asic lock doesn't disable the ram. So if you did unlock, enable ram, lock, then it will still be visible and you can read/write it.
However, now you can't disable it without unlocking the asic.
* all features, if programmed, remain active after lock, un-locking etc. They don't get cleared.
Note: As one may see, the nybbles in the sequence are based on two 4bit shift registers. For one reason or another, Amstrad has patented the verification mechanism ([[Media:Patent GB2243701A.pdf|GB2243701A]]). The patent seems to focus on ''verifying'' (rather than on ''sending'') the sequence, so its legal use is a bit unclear.
