Changes
/* Clock sequence */
Because that can auto-generate bad unwanted sub-clocks...
In fact, it's better to create each CLK and not(CLK) from DCM, in this case you enter in time constraintsnorm, and then rules/checks are done on every _edge instruction. Choosing only one sort of _edge (rising or falling) seems better also. Using that way you just have more "bad compiling error" shown, helping you creating a better code.
It seems also better (to create each CLK and not(CLK) from DCM) in order to solve the "magic" ramb16_s16_s16 component time equations (two differents clocks in entry of this component are making a certain clock equation solved automatically by common DCM - smaller common divisor)
