Changes
/* Test of a real Zilog 80 */
[[http://www.youtube.com/watch?v=YYnvkR5v3D0 http://www.youtube.com/watch?v=YYnvkR5v3D0]]
For it I plug all wires simply from 1 to 40. Some wires are cut, some are Vcc, others GND. Z80 output are directly connected, Z80 input are pull-up with red-red-red resistors (I like red), Z80 is powered 5v (pmod can give 5v using jumper). In fact z80 is so old component that powering it 5v do does output 3.3v.
In fact the only difference between [[T80]] of opencore and real Z80 is that [[T80]] run on rising_edge, and Z80 run during low state. Test past with little modification of sequencer forcing it do nothing during low state of z80, resulting a downclock (memory is too overclocked with this sequencer modification), perhaps using buffer on address bus and data bus could solve this detail... but as it runs for me it is not a problem.
