Changes
/* Instruction timing : talk about r005.8.16c29 */
==== Instruction timing : talk about r005.8.16c29 ====
This version does implements correctly a theorical WAIT_n generator : I used a script comparing Z80 doc timings to plustest.dsk testbench result on real CPC, I deduce that inserting each time 2 WAIT_n does the stuff. I also revisited the edges of WAIT_n generator, to insert WAIT_n at 2T.
I also removed the edge detection of IO_ACK on gatearray, replacing it by state detection of IO_ACK, resulting cpctest's testbench back : this test of HSYNC width is now successfull.
plustest.dsk has some "missing tests" but in fact there are the prefixes : CB, DD, ED, FD, used to launch other areas of instructions.
Megablaster seems running fine in r005.8.16c29.
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