*[https://github.com/MicroCoreLabs/Projects MCLZ8] [https://github.com/rejunity/z80-open-silicon z80-open-silicon] Z80 emulators to be used as drop-in replacement
*[https://github.com/nukeykt/Nuked-MD-FPGA/blob/main/z80.v Nuked-MD-FPGA] [https://github.com/gdevic/A-Z80 A-Z80] Verilog Z80 implementations reverse engineered from decapped chip [https://baltazarstudios.com/z80-ground/ Baltazar] [https://www.righto.com/2014/10/how-z80s-registers-are-implemented-down.html Ken Shirriff] [https://static.righto.com/files/z80-pla-table.html Instruction decode PLA table] Technical documentation
*[https://github.com/floooh/v6502r Visual Z80 Remix] [https://github.com/gdevic/Z80Explorer Z80 Explorer] Netlist-level ultra accurate Z80 simulators
*[https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/gate-array-decapped! Forum thread] Reverse engineered Gate Array by Gerald from decapped chips [https://pastebin.com/ZQyL68Hv Ash Evans] [https://github.com/MiSTer-devel/Amstrad_MiSTer/tree/master/rtl/GA40010 Gyorgy Szombathelyi] [https://github.com/codedchip/AMSGateArray AMSGateArray] Subsequent Verilog/VHDL implementations [https://bread80.com/2021/06/03/understanding-the-amstrad-cpc-video-ram-and-gate-array-subsystem/ Signals analysis by Bread80]