On CPC, bus arbitration occurs on every CPU bus access. The [[Gate Array]] asserts the /WAIT pin on the Z80 for 3 out of every 4 cycles, effectively aligning all operations to a 4-tick cycle.
The NOPs column corresponds to CPC timings, which account for the bus arbitration managed by the [[Gate Array]]. The NOP instruction takes 4 cycles. This is the minimum amount of cycles an instruction can take.
Every M-cycle that involves a memory or I/O access will stretch the previous M-cycle due to bus arbitration. But beware, some M-cycles are purely internal and don't involve a memory or I/O access. So those won't stretch the previous M-cycle.