* Extra: many instructions contain extra T-states necessary for computations. In the official CPU documentation, these are sometimes identified as a separate M-cycle, and sometimes just lumped together with other M-cycle types. For example:
**The INC pp instruction has only one M-cycle, but consisting of 6 T-states instead of the usual 4.
**The instruction RST t has an M1 cycle consisting of 5 T-states instead of the usual 4.
**The CALL cc,nn instruction has an extra T-state inserted in M3 depending if cc is true or not.