Changes

FPGAmstrad

4 bytes added, 18:27, 11 October 2017
/* State machine */
Using VHDL, I implements state-machine using a simple "switch case" on an '''integer'''. and before break I just change (increment...) this integer variable value, changing line of "switch case" this way.
This "switch case" is encalupsed on a "if do/done do/done do/done" instruction. "do " being a boolean from MASTER, and "done " being a boolean from SLAVE. Each MASTER against SLAVE component has a "do" (input if SLAVE component, output if MASTER component) and a "done" (input if MASTER component, output if SLAVE component) wire.
That's all. Like this you can run several sequential instructions, like reading and interpreting severals FAT32 variables using a SPI slaved component solving "read one byte at this address" turned into low-level SDCARD protocol language.
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