GBZ80
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Revision as of 05:10, 23 April 2025 by Phi2x (Talk | contribs) (Created page with "* The Nintendo documentation does not mention M-cycles or T-states at all. They only mention CPU cycles, which are always equal to 4 T-states (like NOPs in the CPC world). Als...")
- The Nintendo documentation does not mention M-cycles or T-states at all. They only mention CPU cycles, which are always equal to 4 T-states (like NOPs in the CPC world). Also, the GBZ80 has different timings than the Z80. For example, CALL nn takes 6 cycles on the GBZ80, but only 5 NOPs on the Z80. Gameboy programming manual
- The GBZ80 lacks the alternate register set, the dedicated I/O bus, the R register, the index registers (thus no DD and FD prefixed opcodes), the ED prefixed opcodes (including block transfer), the sign and parity/overflow flags (and all conditional instructions that used them), the undocumented flags (thus no leaking of WZ and Q internal registers). GBZ80 opcodes
- The GBZ80 also lacks the NMI pin (thus no IFF2 and no RETN), the IM instructions and the I register. It has a different interrupt system than the Z80. Source
- Fun fact: Way more GBZ80 cores were produced for Gameboy hardware (118 million Gameboys and 81 million GBA) than all the Z80 chips produced for home computers and game consoles. Learn GBZ80 Assembly Programming with ChibiAkumas
