**The instruction RST t has an M1 cycle consisting of 5 T-states instead of the usual 4.
**The CALL cc,nn instruction has an extra T-state inserted in M3 depending if cc is true or not.
{| class="wikitable"
|+ The Z80 Machine Cycles and Control Signals
! Machine Cycle !! MĖ
â !! MREQ !! IORQ !! RD !! WR
|-
| Opcode Fetch || 0 || 0 || 1 || 0 || 1
|-
| Memory Read || 1 || 0 || 1 || 0 || 1
|-
| Memory Write || 1 || 0 || 1 || 1 || 0
|-
| I/O Read || 1 || 1 || 0 || 0 || 1
|-
| I/O Write || 1 || 1 || 0 || 1 || 0
|-
| Interrupt Acknowledge || 0 || 1 || 0 || 0 || 1
|-
| Non-maskable Interrupt || 0 || 1 || 0 || 0 || 1
|-
| Bus Acknowledge || 1 || Z || Z || Z || Z
|}
Note: 0=Active, 1=Inactive, Z=High Impedance
<br>