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The [[Z80|Z80]] CPU contains several undocumented opcodes, which can be quite helpful sometimes. The most useful undocumented opcodes are probably these ones, which split up the 16bit index registers IX and IY in 8bit registers called IXL,IXH,IYL and IYH.

Please note, that many Z80 successors like the Z180 are NOT able to execute some of the following opcodes properly.

This is just an overview. Parts of this article have been copied from the [http://www.robsymyquest.netnl/z80undocumented/z80undoc.pdf "The Undocumented Z80 Documented" ] originally by Sean Young]and currently maintained by Jan Wilmans, which is one of the most comprehensive descriptiondescriptions around.

== CB prefix ==

The following Of the 247 opcodes that use the prefix &CB, the block &CB &30 to &CB &37 is undocumented officially. These commands set shift the operand register left and set its lowest bit to 1 instead . This is in contrast to 0:SRL (Shift Right Logical), which shifts right and clears the highest bit. Some believe these opcodes were supposed to be Shift Left Logical but that the setting of the lowest bit represents a bug in the Z80, claiming this is why the opcodes are undocumented. Others call the opcodes SLIA, for Shift Left Inverted Arithmetic. Regardless of the story behind this operation, its effective result is ''register'' = (''register'' * 2) + 1, something that does have its uses and has been employed in various programming contexts for that reason. <pre>CB30 SLL B

== DD and FD prefixes ==

The &DD/or &FD prefixes replace are documented as causing operations using the 16-bit register HL to instead work with either of the 16-bit indexing registers L, H IX or IY; if the operations access a memory location (''i.e.'' normally LD A,(HL with IXL), ''etc.''), the opcodes must additionally include an extra byte that specifies a signed displacement (-128 to +127) from IX/IYLIY. However, Zilog have not documented the fact that these prefixes also affect opcodes that usually refer to the 8-bit components of HL, ''i.e.'' H and L. Thus, one gains access to the additional registers IXH/, IXL, IYH , and IYL, for almost all commands that normally use H or L. It is even possible to do things like LD IXH,IXL (although you cannot combine IX/and IYin the same instruction, for obvious reasons). These registers can be useful in routines that must process and/or store a lot of numbers. Thankfully, they are not as slow as their 16-bit counterparts: whereas access to (IX+d) is usually slower by 3 NOPs than the equivalent operation upon (HL), using the 8-bit components is (like PUSH IX, ''etc.'') only 1 NOP slower, and this is only due to the need to parse the prefixing byte. <pre>DB #DD:LD H,A -> &gt; LD IXH,ADB #FD:LD B,L -> &gt; LD B,IYL</pre>Note: These registers are called LX, LY, HX, and HY by [[WinAPE]]'s debugger, although its assembler uses the names given above.

== ED prefix ==

There are a number of undocumented EDxx instructions, of which most are duplicates of documented instructions. Any instruction not listed has no effect (same behaviour as 2 NOP instructions).

The complete list except for the block instructions:<pre>ED40 IN B,(C) ED60 IN H,(C)

</pre> == DDCB prefix == The undocumented DDCB instructions store the result (if any) of the operation in one of the seven all-purpose registers, which one depends on the lower 3 bits of the last byte of the opcode (not operand, so not the offset).

The undocumented DDCB instructions store the result (if any) of the operation in one of the seven all-purpose registers, which one depends on the lower 3 bits of the last byte of the opcode (not operand, so not the offset). <pre>000 B

</pre> The documented DDCB0106 is RLC (IX+01h). So, clear the lower three bits (DDCB0100) and something is done to register B. The result of the RLC (which is stored in (IX+01h)) is now also stored in register B. Effectively, it does the following:<pre>LD B,(IX+01h)

</pre>So you get double value for money. The result is stored in B and (IX+01h). The most common notation is: RLC (IX+01h),B

I’ve once seen this notation:<pre>RLC (IX+01h)

</pre>That’s not correct: B contains the rotated value, even if (IX+01h) points to ROM. The DDCB SET and RES instructions do the same thing as the shift/rotate instructions:<pre>DDCB10C0 SET 0,(IX+10h),B

</pre>So for example with the last instruction, the value of (IX+10h) with bit 0 set is also stored in register A.

So for example with the last instruction, the value of (IX+10h) with bit 0 set is also stored in register A. The DDCB BIT instructions do not store any value; they merely test a bit. That’s why the undocumented DDCB BIT instructions are no different from the official ones: <pre>DDCB d 78 BIT 7,(IX+d)

</pre>== FDCB prefix ==

== FDCB Same as for the DDCB prefix ==, though IY is used instead of IX.

* [http://www.myquest.nl/z80undocumented/z80-documented-v0.91.pdf "The Undocumented Z80 Documented" by Sean Young Version 0.91, 18th September, 2005] at [http://www.myquest.nl/z80undocumented/ Jan Wilmans' Website] * {{BrokenLink|http://www.grimware.org/lib/exe/fetch.php/documentations/devices/z80/z80.memptr.eng.txt|2017|01|22|21|32|33|text== Web links ==Short information about the internal "MEMPTR" 16bit register of the Z80 and its influence on the F-Register}}