Changes
/* Clock sequence */
Because that can auto-generate bad unwanted sub-clocks...
==== Mirror VRAM Clock sequence : under time constraints (quality) ====In order to get a better external RAM performancefact, it's better to create you clock sequencer '''wiring each CLK and getting more luck about porting my project into others FPGA platformnot(CLK) directly from DCM''', in this case you enter in time constraints norm, I do now use a "Mirror VRAM" : external is just used by Z80 read and writethen rules/checks are done on every _edge instruction. And a write in video RAM zone Choosing only one sort of _edge (like "poke &C000,255"rising or falling) does just write seems better also in another parallel RAM, a FPGA internal RAM, . Using that I call VRAMway you just have more "bad compiling error" shown, this VRAM can be written at helping you creating a certain speed and read at another for VGA purpose (FPGA internal RAM can be used like that)better code.
==== Clock sequence using '''counter plugged with a clock''' was in fact out of law : Mirror VRAM (but running fine in my first versions of FPGAmstrad as I'm a good blind developerperformance)====In order to get a better external RAM performance, because output are not under clock constraint : just think and getting more luck about that porting my project into others FPGA platform, I do now use a "notMirror VRAM" component added : external is just after a used by Z80 read and write (no more clock wire is out of -time constraints- law.sequence finally ^^').. destroying And a write in video RAM zone (like "time constraintpoke &C000,255" solver (the one telling you when your code is bad ) does just write also in another parallel RAM, a FPGA internal RAM, that I call VRAM, this VRAM can be written at a certain speed and read at another for VGA purpose (FPGA internal RAM can be better)used like that)
=== How to tickle JavaCPC ===
