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PWM

288 bytes added, 12:29, 11 March 2018
Pulse Width Modulation, is a DAC (Digital Analog Convertor) using only numerical components (outputting only 0v or 5v values)<br />Using a an entry clock, you output a signal several signals 0v or 5v in order to result an average fix value between 0v and 5v, for sample 2.3v. Changing like it the speed of a small electric motor (speeding it up or slowing it down) as you want but using at input its inputs only two values : 0v or 5v.<br />
Using a quicker clock, you can generate analog signal, like sound music.
entity PWM is
port (
clk : in std_logic;-- 1MHz : same one as sound chip clk
PWM_in : in std_logic_vector (7 downto 0) := "00000000";
PWM_out : out std_logic
end PWM_arch;
Ok, let's go further, let's target 2.5v using only 0v and 5v, with a stupid slow clock, you result in a sequence like this : 05050505050505v. It is has a bad border effect : it 's a noise ! 2.5v normaly doesn't produce sound by here, but using this simple PWM it does.<br />
This problem is solved here : this is an original homemade PWM component enabling Arkanoid not producing noises instead of silents, don't ask me how I solved it two years ago but it does :
-- {@ {@{@{@{@ {@ CoreAmstrad is implementation of FPGAmstrad on MiST-board
-- {@{@ {@{@ Contact : renaudhelias@gmail.com
-- {@{@{@{@{@{@{@{@ @see httpshttp://github.com/mist-devel/mist-board/wiki
-- {@{@{@{@{@{@ @see FPGAmstrad at CPCWiki
--
entity PWM is
port (
clk : in std_logic;-- 50MHz : higher than dog and cat frequency, a multiple of clk_ref clk_ref : in std_logic;-- 1MHz : same one as sound chip clk
PWM_in : in std_logic_vector (7 downto 0) := "00000000";
PWM_out : out std_logic
PWM_out <= PWM_Accumulator(8);
end PWM_arch;
 
[[Category:Hardware]]
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