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8251 USART chip

51 bytes added, 12:23, 5 August 2010
/* Registers */
=== Control Register (W) ===
The first write after internal or external Reset is the "Mode Instruction":
Bit Expl.
0-1 Baud Rate Divider (0=Sync Mode, 1=Div1, 2=Div16, 3=Div64)
2-3 Character Length (0=5bit, 1=6bit, 2=7bit, 3=8bit)
3rd write - Sync Character 2
All further writes to the Control Register are "Command Instructions":
Bit Expl.
0 Transmit Enable (0=Disable, 1=Enable)
1 Data Terminal Ready (0=No, 1=Yes) (DTR Pin)
=== Status Register (R) ===
Bit Expl.
0 Transmit Ready (0=Busy, 1=Ready; "DB Buffer Empty")
1 Receive Ready
=== Data Register (R/W) ===
Bit Expl.
0-7 Data
 
== 8251 vs 8251A ==
6,388
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