Changes
CRTC
,* See the document "Extra CPC Plus Hardware Information" for more details.
=== Horizontal and Vertical Sync (R3) ===
UM6845:
Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16.
=== Interlace and Skew (R8) ===
UM6845:
[[File:CRTC Interlace modes.png]]
=== UM6845R and R31 ===
R31 is described in the UM6845R documentation as "Dummy Register".
R31 doesn't exist on types 0,2,3,4.
=== UM6845R and R12/R13 ===
The UM6845R differs to other CRTC in respect of R12/R13.
In demos to make a display compatible with all CRTCs program R12/R13 when VCC!=0. This will then take effect at the next frame start.
=== UM6845R status register ===
The UM6845R has a status register that can be read using port &BExx.
All the other bits read as 0 and don't have any function.
=== ASIC/Pre-ASIC and R10/R11 ===
The cursor raster registers R10/R11 act as status registers on Types 3 & 4.
{| class="wikitable sortable"
! R10 - Bit number
! Bit value
! Event
|-
|0
|1
|C0=R0
|-
|1
|0
|C0=R0/2
|-
|2
|0
|C0=R1-1 (if R0>=R1)
|-
|3
|0
|C0=R2
|-
|4
|0
|C0=R2+R3
|-
|5
|0
1
|R3h>0 : C0=0..R0 on the line R3h from Vsync (C4=R7)
R3h=0 : C0=0..R0 over 15 lines from Vsync (C4=R7)
|-
|6
|1
|Always 1
|-
|7
|0
0
|C0=0..R0-1 : VMA.Lsb=0xFF
C0=R0 : VMA'.Lsb=0x00 (same cond if C0=R0=0)
|}
{| class="wikitable sortable"
! R11 - Bit number
! Bit value
! Event
|-
|0
|0
|C4=R4 and C9=R9 and C0=R0 : Last char of screen
|-
|1
|0
|C4=R6-1 and C9=R9 and C0=R0 : Last char displayed
|-
|2
|0
|C4=R7-1 and C9=R9 and C0=R0 : Last char before Vsync
|-
|3
|0/1
|Timer 16 CRTC frames
|-
|4
|1
|Always 1
|-
|5
|0
|C9=R9 : C0=0 to R0
|-
|6
|0
|Always 0
|-
|7
|1
|(C9=R9 and C0=R0) or (C9=0 and C0=0 to R0-1)
|}
== CRTC Timing Diagram ==
[[File:CRTC timing small.gif]]
== Internal Counters ==
|''Used for interlace and CRTC cursor blinking''
|}
== Hitachi Block Diagram ==
[[File:CRTC Block Diagram.png]]
== UMC Block Diagram ==
[[File:UMC CRTC Block Diagram.png]]
== Motorola Block Diagram ==
[[File:Motorola CRTC Block Diagram.png]]
== Datasheets ==
