Changes
/* Amplitude Control (Registers R10,R11,R12) */ fixed table format
== DESCRIPTION ==
The [[AY]]-3-8910/8912/8913 Programmable Sound Generator (PSG) is a LSI Circuit which can produce a wide variety of complex sounds under software control. The AY-3-8910/8912/8913 is manufactured in the General Instrument N-Channel Ion Implant Process. Operation requires a single +5V power supply, a TTL compatible clock, and a microprocessor controller such as the General Instrument 16-bit CP1610 or one of the PIC1650 series of 8-bit microcomputers.
The PSG is easily interfaced to any bus orientation system, its flexibility makes it useful in applications such as music synthesis, sound effects generation, audible alarms, tone signalling and FSK modems. The analog sound outputs can each provide 4bits of logarithmic digital to analog conversion greatly enhancing the dynamic range of the sounds produced.
|colspan=4|NOT USED||TP11||TP10||TP9||TP8||TP7||TP6||TP5||TP4||TP3||TP2||TP1||TP0
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|colspan=4| ||colspan=12|12-bit Tone Period (TP) to Tone Generator
|}
{|{{Prettytable|width: 700px; font-size: 2em;}}
|-
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|colspan=3|NOT USED||colspan=5|5-bit Noise Period (NP) to Noise Generator
|colspan=3|NOT USED||M||L3||L2||L1||L0
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|colspan=3|||amplitude "mode"||cospancolspan=4|4-bit "fixed" amplitude level
|}
Registers R16 and R17 function as intermediate data storage registers between the PSG/CPU data bus (DA0--DA7) and the two I/O ports (IOA7--IOA0 and IOB7--IOB0). Both ports are available in the AY-3-8910; only I/O port A is available in the AY-3-8912; none are available on the AY-3-8913. Using registers R16 and R17 for the transfer of I/O data has no effect on sound generation.
== D/A Converter Operation ==
Since the primary use of the PSG is to produce sound for the highly imperfect amplitude detection mechanism of the human ear, the D/A conversion is performed in logarithmic steps with a normalized voltage range of from 0 to 1 Volt. The specific amplitude control of each of the three D/A Converters is acomplished by the three sets of 4-bit outputs of the Amplitude Control block, while the Mixer outputs provide the base signal frequency (Noise and/or Tone).
|0||0||x||x||[[Image:psg1.gif]]
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|0||1||x||x ||[[Image:psg3.gif]]
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|1||0||0||0 ||[[Image:psg5.gif]]
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|1||0||0||1 ||[[Image:psg1.gif]]
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|1||0||1||0 ||[[Image:psg8.gif]]
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|1||0||1||1 ||[[Image:psg4.gif]]
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|1||1||0||0 ||[[Image:psg6.gif]]
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|1||1||0||1 ||[[Image:psg2.gif]]
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|1||1||1||0 ||[[Image:psg7.gif]]
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|1||1||1||1 ||[[Image:psg3.gif]]|-|colspan=4| ||[[Image:psg15.gif]] |} '''Fig 2. DETAIL OF TWO CYCLES Of Fig 1 (ref. waveform "1010" in Fig.1)'''
'''Fig 3. D/A CONVERTER OUTPUT'''
'''Fig 4. SINGLE TONE WITH ENVELOPE SHAPE/CYCLE PATTERN 1010'''
'''Fig 5. MIXTURE OF THREE TONES WITH FIXED AMPLITUDE'''
== ELECTRICAL CHARACTERISTICS (AY-3-8910, AY-3-8912) ==
Exceeding these ratings could cause permanent damage to the device. This is a stress rating only and functional operation of the devices at these conditions is not implied -- operating ranges are specified in Standard Conditions. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Data labelled " typical" is presented for design guidance only and is not guaranteed.
'''Storage Conditions (unless otherwise noted):'''
Vcc = ± 5V ±5%
Operating Temperature = 0°C to +40°C
{|{{Prettytable|width: 700px; font-size: 2em;}}|'''Characteristics'''||'''Sym'''||'''Min'''||'''Typ**'''||'''Max'''||'''Units'''||'''Conditions'''|-|'''DC CHARACTERISTICS '''|-|'''All inputs '''|-|Low level ||Vil ||0 ||- ||0.6 ||V |-|High level ||Vih ||2.4 ||- ||Vcc ||V |-|'''All Outputs (except Analog Channel Outputs '''|-|Low level ||Vol ||0 ||- ||0.5 ||V ||Iol = 1.6mA, 20pF |-|High level ||Voh ||2.4 ||- ||Vcc ||V ||Ioh = 100uA, 20pF |-|Analog Channel Outputs ||Vo ||0 ||- ||60 ||dB ||Test Curcuit: Fig 6 |-|Power Supply Current ||Icc ||- ||45 ||85 ||mA |-|'''AC CHARACTERISTICS '''|-|'''Clock Input '''||Fig 7. |-|Frequency ||fc ||1 ||- ||2 ||MHz |-|Rise Time ||tr ||- ||- ||50 ||ns |-|Fall Time ||tf ||- ||- ||50 ||ns |-|Duty Cycle ||- ||25 ||50 ||85 ||% |-|'''Bus Signals (BDIR,BC2,BC1) '''|-|Associative Delay Time ||tao ||- ||- ||50 ||ns |-|'''Reset '''Fig. 8 |-|Reset Pulse Width ||trw ||500 ||- ||- ||ns |-|Reset to Bus Control Delay Time ||trb ||100 ||- ||- ||ns |-|'''A9, A8, DA7--DA0 (Address Mode) '''||Fig 9 |-|Address Setup Time ||tas ||400 ||- ||- ||ns |-|Address Hold Time ||tah ||100 ||- ||- ||ns |-|'''DA7--DA0 (Write Mode) '''||Fig. 10 |-|Write Data Pulse Width ||tdw ||500 ||- ||10,000 ||ns |-|Write Data Setup Time ||tds ||50 ||- ||- ||ns |-|Write Data Hold Time ||tdh ||100 ||- ||- ||ns |-|'''DA7--DA0 (Read Mode) '''||Fig. 11 |-|Read Data Access Time ||tda ||- ||250 ||500 ||ns |-|'''DA7--DA0 (Inactive Mode) '''|-|Tristate Delay Time ||tts ||- ||100 ||200 ||ns |}
** Typical values are at ±25°C and nominal voltages
'''Analogue Channel Output Test Curcuit'''
== ELECTRICAL CHARACTERISTICS (AY-3-8913) ==
* Exceeding these ratings could cause permanent damage to the device. This is a stress rating only and functional operation of the devices at these conditions is not implied -- operating ranges are specified in Standard Conditions. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Data labelled " typical" is presented for design guidance only and is not guaranteed.
'''Storage Conditions (unless otherwise noted):'''
Vcc = ± 5V ±5%
Operating Temperature = 0°C to +70°C
{|{{Prettytable|width: 700px; font-size: 2em;}}
|'''Characteristics'''||'''Min'''||'''Sym'''||'''Max'''||'''Units'''||'''Conditions'''
|-
|'''DC CHARACTERISTICS'''
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|'''All inputs'''
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|Low level||Vil||0||0.7||V
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|High level||Vih||2.2||Vcc||V
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|'''All Outputs (except Analog Channel Outputs'''
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|Low level||Vol||0||0.4||V||1||TTL||Load
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|High level||Voh||2.4||Vcc||V||+100pf
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|'''Analog Channel Outputs'''||Vo||0||2000||uA||Test Curcuit: Fig 6
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|'''Power Supply Current'''||Icc||-||85||mA
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|'''AC CHARACTERISTICS'''
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|'''Clock Input'''||Fig 7.
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|Frequency||fc||1||2.5||MHz
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|Rise Time||tr||-||50||ns
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|Fall Time||tf||-||50||ns
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|Duty Cycle||-||40||60||%
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|'''Bus Signals (BDIR,BC2,BC1)'''
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|Associative Delay Time||tao||-||50||ns
|-
|'''Reset'''||Fig. 8
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|Reset Pulse Width||trw||5||-||us
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|Reset to Bus Control Delay Time||trb||100||-||ns
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|'''A9, A8, DA7--DA0 (Address Mode)'''||Fig 9
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|Address Setup Time tas 300 - ns
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|Address Hold Time tah 50 - ns
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|DA7--DA0 (Write Mode)'''||Fig. 10
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|Write Data Pulse Width||tdw||1800||-||ns
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|Write Data Setup Time||tds||50||-||ns
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|Write Data Hold Time||tdh||100||-||ns
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|'''DA7--DA0 (Read Mode)'''||Fig. 11
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|Read Data Access Time||tda||-||350||ns
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|'''DA7--DA0 (Inactive Mode)'''
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|Tristate Delay Time||tts||-||400||ns
|}
'''Fig 710. CLOCK AND BUS SIGNAL WRITE DATA TIMING'''
'''Fig 811. RESET READ DATA TIMING'''
