== Last news about this project ==
In MaY 2020, I add Sorgelig formula for WAIT_n=quick, no more table of instruction time in code, just a simple WAIT_n formula.
In MaY 2019, I add cassette feature.
In August 2018, totally desperated -around time and level of efforts- about reaching next step focus around Z80 range, here came Sorgelig, he is working around port of FPGAmstrad into the MiSTer FPGA platform, and make during his step an intermediate jump step on MiST-board called "Amstrad_MiST" full of verilog as he seems to love. And, as a specialist of Z80 core, I just send him Z80 testbenches I collected since, he then corrected the Z80 fully this way, I merged, resulting this next current checkpoint.
In May 2018, I programmed my first CPC game http://www.pouet.net/prod.php?which=75855 following JDVA youtube tutorial since january, they are based on CPCMania 2005's website knowledge about programing in CPC using SDCC. I think that if I do progress this way enough, I'll implement my own CPC testbenches, needed for reaching next realise of FPGAmstrad (I did it : Moustache testbench)
[[File:Mk2-cpc-600x350.png|thumbnail|Image converted to CPC by SuTeKH/Epyteo]]
In January 2018, Jepalza has ported FPGAmstrad from this wiki (Xilinx version, principe of concept 2011) on spanish ZX-Uno low-cost FPGA final platform (three times cheaper than MiST-board/same Xilinx chip poc 2011/chip used at 100%). So I bought a ZX-Uno to help around this fork, merging components. Normaly I can go a little further later (CRTC0, joystick), and then go back to MiST-board :)
https://www.youtube.com/watch?v=tpr9xxx1rsA
In May 2017, FPGAmstrad TV mode is validated using a TV from Tetalab group.
===On MiST-board CoreAmstrad version===
Games that doesn't run are :
*'''007 The Living Daylight.dsk''': problem with VSYNC. Certainly two VSYNC per frame, GA ignoring the second one.
*'''ACPC_logon_system.dsk''': text scrolling lag. This demo will be used for horizontal ink calibration (when I’ll buy a luxurious FPGA platform... I need in fact 224KB of internal RAM to do it), and CRTC overcounts.
*'''commando.dsk''': pixels that should be deleted are not deleted (only VRAM &C000-FFFF seems used)
*'''split ink demo.dsk''': (from cpcrulez) : may help about ink raster calibration.
*'''Sultan's Maze.dsk''': does need the right part of keyboard (F0-F9 are used for directions in this game)
*'''Orion Primes.dsk''': does display "secteurs entrelacés" - "vérifiez votre copie", a FDC problem, perhaps "sectorId++" is not the good way to reach next sector, or else two tracks in one track. Does pass on Sorgelig fork.*'''Batman_Forever.dsk''': some problem during flying chip demo part (one garbage line), and several rupture showing ghost lines around Vcc=0. Rupture solved in r005.8.16c4, but flying chip now show a half garbage of pixels. Batman seems CRTC1. '''BattroProblems with FDC in r005.dsk''' seems also CRTC1 and does fail completly8.16 (does slow animations, like if I missed some "not ready" signal ?)*'''30YMD.dsk''': in Benediction demo, at bottom some time you see some ghosts of central animation (too many HSync per screen ?), solved in r005.8.16c4 16 (CRTC0 seems perfectly implemented). 30YMD seems CRTC0, running fine except that changing disk feature does still fail.*'''arkanoid2.dsk''': don't run in r005.8.13, but fine in r005.8.13e (experimental fork), ok in r005.8.14 (using default OSD value : MEM_WR=quick)*'''trailblazer.dsk''': no more "raster" problem since r005.5, it's now perfect ! Palette heuristic offset (done for unlocking Batman Forever Demo) has a small effect in left (squares are inserted/not separated by a black line in first column) - same small defect in TV mode using r005.8.14.2... Thinking about a HSYNC offset of 2 (instead of 1 currently) then also delaying DATA+HDISP of 1 (charinserted/inserted signal ?)*'''imperial_mahjong.dsk''': modern EXA/EXA2 resolution not passing my color pallet heuristic :p- does pass on Sorgelig fork.
*'''rtypeee.dsk''': at begin of presentation, a draw of "jack plug" is done in a strange video mode, more than 200 pixels of height !, see [http://cpc.sylvestre.org/musee/musee_flipping_lace.html flipping lace]
*'''S&Koh.dsk''': LOGON SYSTEM, black screen in r005.8.4... damn
*'''Pinball_Dreams__PREVIEW.DSK''': Does run in experimental/ versions r005.8.9.2 and r005.9.11e (experimental forked version of r005.9.11 using flag FPGAmstrad_amstrad_motherboard.vhdl.HACK_Z80=false). Does freeze in !experimental versions when background music is special (not long classic background music) and you press two buttons (left/right flipper keys) at the same time, ok in r005.8.14 (using default OSD value : MEM_WR=quick). Scrolling text is OK in r005.8.16c4 but still one garbage line at top of main game (CRTC1 offset ?)
*'''Fres Fighter II Turbo.dsk''': FDC problem, cannot be launched.
*'''Seascape.dsk''': Devilmarkus, using scandb50Hz and MEM_wr=slow, does display, but a flower petal at bottom is drawn in blue. A good raster test. Test on real 6128 [http://www.cpcwiki.eu/forum/demos/seascape-cpc-by-impact-on-original-cpc-6128/ forum: Seascape CPC by Impact - on original CPC 6128 ?] - by Emashzed : type 1 is perfect (no blue on bottom right flowers, no blue on middle triangle rock), type 2 has bright cyan squares (one on bottom right flowers, and one on middle triangle rock. Calibrated OK in r005.8.16.5 using OSD VGA:scandb50Hz. Does pass on Sorgelig fork.
[[File:Seaspace-type1_MiST-board_CoreAmstrad-r005.8.16.5|thumbnail|Seascape (type 1) - r005.8.16.5]]
*'''Megablasters[original].dsk''': has a 2 pixels glich border on left side. Certainly final HSYNC offset problem, as on Super Cauldron normaly the right (not left) border has to be selected to get a nice bottom bar in game (actually too centered)
*'''Edge_Grinder.dsk''': screen not stable horizontally, music change speed during game ? Does pass on Sorgelig fork.
*'''Welcome To Amstrad CPC 6128.dsk''': does display "Incompatible BASIC installed" message.
*'''phX.dsk''': does begin to pass on r005.8.16. Does pass completly on Sorgelig fork (scandoubler). Does finish on amstrad_180804_r005.8.16.5. Does show vertical bars with CRTC0, no display during end scroll part. Does freeze at middle on amstrad_180804_r005.8.16.6 (doesn't launch the read of disk), does pass on Sorgelig fork but song is 2 times slown down before reaching this part. Did pass one time on amstrad_200527_r005.8.16.8.5c1.rbf (CRTC0 WAIT_n:quick (Sorgelig GA simple formula)), but I was lucky. Did pass one time on amstrad_200527_r005.8.16.8.5c2.rbf (CRTC1 WAIT_n:quick) except vertical bars of begin. Seems that launching Pinball Dreams CRTC1 (until menu of boards) before (soft reset (page up key) and) PhX CRTC0 does unlock PhX.
*'''Ghouls'n'Ghost.dsk''': does fail on r005.8.16.2 : time going to zero in 3 seconds, is fine in r005.8.15.2, fine also on Sorgelig fork... also unlocked by Sorgelig in r005.8.16.3 !
* '''Ultimate Megademo (Face Hugger).dsk''': First part is better using CRTC0. Ending part (one just after Lemmings part), a double VSYNC problem (a small scrolling text instead of... a lot of things), music OK during this ending.
'''Arkanoid.dsk''' stars use rupture address (changing address several time during display of one image), it is now supported on "candidate 001" version of FPGAmstrad. Run better in r005.9.11e than in r005.9.11.
'''Ghouls'n'Ghost.dsk''' / '''Ecole.dsk''' does need RAM write when writing in ROM (RAM is beside ROM, hard to emulate with asynchronous SDRAM controler, MiST does use a hacked synchronous RAM done for that)
'''moktar.dsk''' / '''super_cauldron.dsk''' does run fine since r004.8.1.1. Morkar run fine in r005.8.16c4 using CRTC0 and MEM_wr=slow. Super Cauldron bottom bar is fine in r005.8.16.4 when we select "right border" (instead of default left one) during "screen synchro" menu welcome.
'''CPC Aventure''' does run fine since r005.2 (message about turning disk now displayed)
'''-circles.dsk''': this demo freeze does since r004.8 (PPI border effect ?) and is back since r005.5, it was nice to calibrate SOUND clock : I did generate 8 candidates of synchronizing this clock (1MHz from 4MHz : 1100 0110 0011 1001, and 0.5 deltas : 1100i, 0110i, 0011i, 1001i), only one does not freeze -circles... so I release r005.5 candidate. This demo is a great one around calibrating Yamaha clock.
'''Nigel Mansell's Grand Prix.dsk''': Only one race track seems ok : Monaco (Brazil track does not start). Unclassified : this disk bug also with other emulators, certainly a bad dsk dump here, TOSEC version of Nigel Mansell does run fine (but some legendary traces of "SK bit purpose" needed by here (in FDC, setting SK does jump deleted disk tracks), perhaps to investigate) - update : some tracks unlocked in r005.8.15c61.
'''tetris95.dsk''' : bad in r005.8.9.2 (4 beep while breaking 3 lines (instead of 3 beep while breaking 3 lines), was correct in r005.8.4. Back since r005.8.10.
'''Battro.dsk''' seems also CRTC1 and does fail completly. Does pass in r005.8.16.
'''arkanoid2.dsk''': don't run in r005.8.13, but fine in r005.8.13e (experimental fork), ok in r005.8.14 (using default OSD value : MEM_WR=quick)
'''trailblazer.dsk''': no more "raster" problem since r005.5, it's now perfect ! Palette heuristic offset (done for unlocking Batman Forever Demo) has a small effect in left (squares are not separated by a black line in first column) - same small defect in TV mode using r005.8.14.2... Thinking about a HSYNC offset of 2 (instead of 1 currently) then also delaying DATA+HDISP of 1 (char) . Has defect on bottom scroll text bar r005.8.16.2, is fine in r005.8.15.2, fine also on Sorgelig fork... also unlocked by Sorgelig in r005.8.16.3 !
'''commando.dsk''': pixels that should be deleted are not deleted (only VRAM &C000-FFFF seems used), on level 1, the moto is not displayed correctly inside the bridge... but after the bridge :/ - unlocked by Sorgelig in r005.8.16.3 !
'''Pinball_Dreams__PREVIEW.DSK''': Does run in version r005.8.16.6 using CRTC1 (and WAIT_n=slow). Sorgelig fork does implement interlace (used an welcome screen - eagle)
{| class="wikitable"
*To test also : [http://www.speccy.pl/archive/prod.php?id=335 Unlimited Bobs (Dr.Piotr).dsk] demo.
== Effort done =On MiST-board CoreAmstrad version - TAPES ===
=== Instruction timing ===https://cpcrulez.fr/GamesTest/legend_of_steel.htm :I tested instruction timing of [[T80]] compare to instruction timing of JavaCPC emulator Hello, a nice game, unfortunately graphic error at 50 and 72 Hz. I deduce synchronization of Z80 with CRTC My monitor can be 50Hz. 48Hz not. Why does the game show 48Hz on M1 signal by WAIT_n insertion in order to have a multiple of 4 Tstates per instructionmy monitor? https://cpcrulez. I deduce also one WAIT_n inserted during MEM_WR operation (yes I log testbench [[T80]]fr/GamesTest/legend_of_steel.htm Best regards, I’m crazy)MiC
I just made a test bench log List of [[T80]] known running TAPE games (log of instructionon r005.8.16.8.3c9): A Magician s Apprentice (txt), A Message from Deep Space (txt), A View To A Kill, Aaargh!, '''Academy''' (missile commander 360°), Advanced Destroyer Simulator, Advanced Lawnmoving Simulator (by '''DevilMarkus'''), After Shock (txt+img), '''Aftermath''' (missile commander), Air Attack, Air Traffic Control - Heathrow, Air Traffic Control - Schiphol, '''Airborne Ranger''' (aircraft or walk), Airwolf, Aladdin s M1Cave, and first M1 coming after knowing that I send '''Alex Higgins World Snooker''' (pool table), Algebre, Ali Candil Y El Teroso dde Sierra Morena, Alien TurboAmstrad, Alien Syndrome, Aliens The Computer Game, '''Alkahera''' (spacecraft simulator), Alpine games, Alsim, Alternative World Games, Amaurote, Amsgolf, AmstradMagazine Le Survivant, Amstrad Shuffle (card games), Amstrad Tecla a lot Tecla, Amstroid (txt), '''Amstroids''', Angelique A Grief Encounter (txt), '''Angleball''' (pool table), Animal Vegetable Mineral, Annals of NOP after my instructionRome, Antalex (txt), and compare it to a JavaCPC timing array. Some instructions was not tested '''All Points Bulletin''' (interrupt waitlittle car), Apocalipsis New (txt), Arcade Fruit Machine, Arcos, Ariane, Arnhem, '''Asphalt''', Assault Course, Asterix and special timing the Magic Cauldron, Astro Plumber, '''Atahualpa''' (instructions with change timingangel), '''Athlete''', Atlantida 3000 (platform), but all others passed correctlyAtlantis Anirog, Atlantis (txt), '''Atomic Battle''' (asteroids), '''Atomic Driver''' (little car), Auftraq In Der Bronx (txt), Aufwarts Zur Rettung (donkey kong), '''Avenger Way of the Tiger II''', Aventure Au Chateau (adventure), '''Azar Menu''',Abu Simbel Profanation, Ace of Aces, Advanced Pinball Simulator (CPC-Power), After The War, Afteroids (CPC-Power), Agent X 2, Alien Highway, American Football, Amo Del Mundo, Amsgolf, Amsoccer (del key to launch party), Amstrad Unlocked, Animated Strip Poker, Aquad, Arkanoid, Arkanoid II, Arkos, Army Moves, Artura, Ashkeron (txt), Atlantis Anirog, Atom Ant, Auf Wiedersehen Monty, Autocrash, Auxilio Aereo.
==== Instruction timing Games that doesn't run are : currently * '''Action Force.cdt''': freeze during loading, black screen with green border, nothing more. glitch in r008r005.58.14 ====16.8.3c8In GA* '''Adidas Championship Football.cdt''': freeze after loading.* '''Afterburner.cdt''': nothing after load (still black screen with colorfull border) reboot* '''Alien Attack.cdt''': simple tape, I do use begin but freeze (idFF : end of edge tape) saying "is loading". Same using WinAPE.* '''Alien Legion.cdt''': not enough in line 19 : memory &9FFF. Run in r005.8.16.8.3c9 but no key ?* '''Alta Tension.cdt''': 007 Living in fact, same vsync problem than disk version.* '''AMC Astro Marine Corps.cdt''': welcome picture not drawn completely, do load data for IO_ACK instead nothing and then freeze.* '''Anatomie.cdt''': end of statetape idFF.* '''Arnold Goes to Somewhere Else.cdt (txt)''': Rewind tape.* '''Atlantida 3000''': welcome picture seems not fully loaded, but game starting. Same in WinAPE.* '''ATV Simulator.cdt''': nothing after load (still black screen with colorfull border), reboot* '''Automec.cdt''': reboot during game (second tape of three)
M1 reached same Back-Tron, Bacterik Dream (puzzle), Bactro (tron), Bactron, Balade Outre-Rhin (txt), '''Ball Breaker II''' (breakout), Ballon Buster (press space to unlock black screen, and another time of IO_ACK are ignored after welcome screen displayed), Barry McGuigan Word Championship Boxing, Batalla de Inglaterra, Batalla Naval, Battle ships, Battle Tank Simulator, '''Batty''' (not M1breakout) , Beat the Clock (scrabble), Behind The Lines (txt), Berks 3, '''Bestial Warrior''' (platform), Beta-2515, '''BeTiled''' (Bejeweled), Better Spelling, Big Trouble in WAIT_n generator.Little China, Blade Runner, Blagger, Blindado, Blitz AmstradAction, Blockbusters, '''Blue Tomb''' (bomberman), BMX Ninja, '''Bob Morane Espacio''', '''Bomb Jack''', Border Harrier (adventure), '''Bosconian 87''' (Asteroids), '''Boulder Dash 3''', Brian Jacks Superstar Challenge (run), Bride of Frankenstein, Bridge (card), Bronx, '''Bubble Bobble 4''', Bubble Dizzy, Buffalo Bill s Rodeo Games, Buggy II, '''Buggy Boy''', Bugs Buster, Bullseye, Bump Set Spike, Bundesliga Manager 3 (tool), Buscate la vida, Business Plus, '''Buster Block''', Ball Crazy, Barbarian, Bataille Pour Midway, Battle for Midway, Beach Buggy Simulator, Bedlam, Beyond the Ice Palace, Bivouac, Black Beard, Blasteroids, Brawn Free (txt), Bruce Lee, Bubble Bobble (2014-06-20), Buitre-Emilio Butragueno Futbol
MEM_WR has an OSD menu choice * '''Back to switch between "quick" and "slow"Reality.cdt''': Rewind tape.* '''Barbarian II.cdt''': black screen blue border. Welcome screen with glitchs* '''Beach Head 2.cdt''': freeze load. Reboot id13* '''Blood Valley.cdt''': welcome screen, "slowRead error b" mode does insert ONE WAIT_n during detection * '''Bomb Jack 2.cdt''': welcome picture not load completely, freeze.* '''Boom.cdt''': load until block 16, then freeze. Reboot at block 21.* '''Booty.cdt''': second welcome screen then freeze. id15 (ear)* '''Boulder Dash 4.cdt''': not a game but a tool kit, * '''Brainache.cdt''': no pause at begin of tape, welcome screen turn into black screen at end of MEM_WRtape (idFF)* '''Bugs. This switch exists because somes games are running in cdt''': "slowRewind tape" mode and others in "quick" mode.message
==== Instruction timing : talk about r008.5.14 ====Cap Horn, Cap sur Dakar, Cavebola, Cedric y los Juguetes Perdidos, '''Chessmaster 2000''', Civil War, Cluedo, '''Cobra''' (snake), Coloric, Concurso, Conflit en l an 2000, Crystann Le Donjon de Diamant
In fact it exists several instruction making MEM_wr, and adding each one ONE WAIT_n does result in different case * '''CORE Anatomie''': end of synchronizationtape idFF.
[http://www.cpcwiki.eu/forum/emulators/cpc'''Dan Dare 1''', Dances With Bunny Rabbits (txt), Danger Adventurer at work (txt), Danger Mouse In Makin, Dark Side, Dark Star, '''Darts''', De la Terre a la Lune, Deactivators, Deadenders (txt), '''Deadly Evil''' (walk platform), Deathkick (right part of keyboard), '''Deathscape''', Dedalos, '''Defcom1''', Demon Attack, Dempsey and Makepeace, Dernier Metro, Desert Rats, Devil s Castle, Diamond Mine, Diamond Mine 2 (same ?), Die Heilige Rustung Des '''Antiriad''', Die Tiefe (txt), Die You Vicious Fish (txt), '''Digger Barnes''', '''Dimension Omega''', Dirk, Dizzy 2 Treasure Island, Dizzy 4 Magicland, Dizzy 5 Spellbound, Dizzy 6 Prince f the Yolkfolk, Dizzy Down the Rapids, Dominoes (keyboard F1-z80-timing/ CPC Z80 timing]F7 + space), '''Doodle Bug''' (pacman+), Doomsdark's Revenge (txt), Dr Jackle and Mr Wide, Dracula (txt), Dragon's Lair, Dragons of Flame, Driller, Druids Moon (txt), Duel A Abilene, Dun Darach, Dungeons Amethyst (txt), Dynamite Dan, DynamixDaley Thompson Super Test 1, Dark Fusion, Death Stalker, Death Wish 3, Desperado, Die Alien Slime, Dizzy Amstrad Action Special Edition, Dizzy Cristal Kingdom, Double Dragon, Dragon Spirit, Dragontorc, Dustin
If it* '''Daleks.cdt''': use of right part of keyboard as arrow (not mapped)* '''Daley Thompson s about managing GA reading pixels, perhaps Olympic Challenge.cdt''': reboot* '''Damas.cdt''': Rewind Tape* '''Dark Sceptre.cdt''': Rewind to 04* '''Dark Man.cdt''': black screen pink border* * on r005.8.16.8.1c3* '''Death Pit.cdt''': welcome screen not only M1 signal are synchronized but also the MEM_RD and MEM_WR accesses at another offsetloaded completely idFF* '''Deliverance.cdt''': black screen pink border, reboot id13* '''Demon s Revenge.cdt''': "Searching 00" freeze* '''Des Chiffres et des Lettres.cdt''': reboot* '''Dick Tracy''': black screen id15 (ear), idFF (end of tape)* '''Dizzy 3 Fantasy World''': black screen* '''Dominator''': black screen pink border* '''Domino''': Rewind tape* '''Don't Panic''': no pause, freeze message "SEARCHING", id15 (ear) idFF (end of tape)* '''Dragon ninja''': welcome screen ok, message "128K MACHINE DETECTED" - "PLEASE WAIT" too long, slower than WinAPE id11 read (datalen=0 does ignore data read ?)* '''Dynamic Duo''': "Searching 00" freeze
[http://amstradE.eu/modules/newbb/viewtopicX.php?post_id=24592 Timings instructions Z80 sur CPC]I.T, Eagle AmstradVideoPlay, '''Eagle''', Edd the duck, Eden Blues, Egg Blitz, El Comecocos, El Cuerpo Humano, El equipo A (A Team), El Formamento, El Foso, El Misterio del Milo, El Prisionero (txt), '''El Secreto de la Tumba''', Electric Fencing, Electro Freddy, Elevator Action, '''Elven Warrior''', Emerald Isle (txt), Emilio Butragueno Futbol, Emlyn Hughes International Soccer, En Busca Del Arca De ma Alianza (txt), Encyclopaedia of War-Ancient Battles, Endurance, Enduro Racer (moto), Enigme a Oxford, '''Enterprise''', '''Equinox''', Escape-Edisoft, Escape from Khoshima (txt), Espacial, Espana-Comunidades Autonomas 1, Espionage, Espionage Island (txt), Euro Boss, Europa Teatro de Operaciones, European 2, European Champions, '''European Soccer Challenge''', Evening Star, Everyone s a Wally, Exolon, Exploring Adventure on the Amstrad (txt), Exterminator, Eye, E-motion, Echelon, El CID, El juego de la Oca, El Ladron del Sol Purpura, El Poder Oscura, Elektra Glide, Elidon, Emilio Butragueno 2, Emilio Sanchez Vicario Grand Slam, Empire, Enchanted, Endzone, European 5, Every Second Counts, Eye Spy
If interruption r52 is regular* '''Eddie Edwards Super Ski''': rewind tape* '''El Caldero Magic''': return to basic during game, even while making bad charset* '''El Capitan Trueno''': slow block load, reboot** on r005.8.16.8.2c12* '''El Gerente''': rewind tape* '''El Jabato''': blue screen, reboot* '''El Laberinto del Sultan''': rewind tape* '''El Tute''': after a continues MEM_WRcertain time doing nothing, interruption "Read error b"* '''Election''': black screen with blue border, message "LOADING: Please Wait"* '''Eliminator''': black screen with blue border* '''Elite''': "Searching 00", id15 (int<=ear), with somes id11 before and after it.* '1''Energy Warrior''': game launched but bad horizontal alignment* '''Er-bert''': "Press PLAY then any key"; end of tape idFF* '''Erik the Viking''' (txt) shall be taken into account above WAIT_n insertions ?: end of tape idFF, no key* '''Escape from The Planet Of The Robot Monsters''': welcome image OK, then black screen border green* '''Eswat-Cyber Police''': Cannot insert face B* '''Execution''': gray screen* '''Exploding Wall''': black screen red border* '''Explorer''': reset to BASIC* '''Express Raider''': yellow screen blue border, message "LOADING: Please Wait"* '''Extreme''': black screen blue border
In Z80 sequence diagramFantasia Diamond (txt), an IO_ACKFederation (+M1txt) is preceded by M1 , Feliz Navidad, '''Fernandez Must Die''', Ferry Captain, Fifth Quadrant, '''Feud''' (singleOK on r005.8.16.8.2c13), Fighter Pilot, Finders Keepers, Fire Ant, Firescape (txt), First Steps With The Mr Men, Flash, Flight Path 737, Flight Simulation, Fluglehrer, Flunky, Fly, Fly Spy, Football manager, Football manager III, '''Forbidden Planet''', Force 4, Forces, Formula 1 Simulator, Formula, Fourth Protocol, Frank Bruno s Boxing, Frank N Stein, Frankenstein (txt), '''Freedom Fighter''', Friss Man, Frontline, '''Frost Byte''', '''Fruity Frank''', Fu-Kung in Las Vegas, '''Fusion 2'''F-1, Fernando Martin Basket Master, Fiendish Freddy s Big Top O Fun, Firelord, First Past The Post, Five a Side Football, Football Champion, Footballer of the year I, Forgotten Worlds, Formula One, Frankenstein Jnr/Junior, Froggy, Fuego Curzado, Future Knight
cpctest.dsk -Timing Instruction- is different while using mode "MEM_WR=* '''F15 Strike Eagle''': black screen blue border, xFF (end of tape)* '''F16 Combat Pilot''': black screen blue border, xFF (end of tape)* '''F16 Fighting Falcon''': light gun game* '''F1 Tornado Simulator''': some vsync problem ?* '''FA Cup Football''': Rewind tape slow" and "MEM_WR=quick"face of tape OK* '''Fairlight 1 A Prelude''': Rewind tape* '''Fast Food Dizzy''': black screen, a dot* * on r005. Strangly better using "MEM_WR=quick"8.16.8.2c13* '''Fighter Bomber''': black screen pink border, reboot* '''Fighting Soccer''': black screen blue border, reboot* '''Fire and Forget 1''': Rewind tape, idFF (end of tape)* '''Firezone''': use right part of keyboard* '''Flash Gordon''': Read error b* '''Flying Shark''': Searching 00, strange id60 (end of tape). Rewind to 12* '''Football Director''': welcome picture not load completely, freeze, xFF (end of tape)* '''Football Frenzy''': Rewind tape* '''Football manager II''': welcome image and music, then Rewind tape* '''Football Manager World Cup Edition''': welcome screen, no more idFF (end of tape)* '''Footballer of the year II''': glitch* '''Freddy Hardest 1''': black screen blue border* '''Freddy Hardest 2''': reboot* '''Freestyle BMX Simulator''': black screen* '''Friday The 13th''': rewind tape at idFF (end of tape)* '''Fruit Machine Simulator''': black screen blue border* '''Fruit Machine Simulator II''': black screen, reboot
Current version is using "Z80_HACK=true" G-LOC R360, '''Galachip''' (parameter set during compilationspace invaders), that shunt Z80.WAIT_n entryGalletron, Garfield 1 & 2, Gauntlet-Micropower, Gazza s Super Soccer, GBA Championship Basketball 2 On 2, Z80.clock is slow down during theses WAIT_n. It'''Geasa-Parabola''', Gem, Geoff Capes Strongman, '''Ghost Hunters''', '''Ghostbusters 1''', Ghostbusters 2, Ghouls, Gilligan s Gold, Glass, '''Glen Hoddle Soccer''', Glider Rider, '''Golf Trophee''', Gorbaf El Vikingo, Graham Gooch s Test Cricket, '''Grand Prix 500cc''', Grand Prix Driver, Great Gurianos, Grell and Falla, Greyfell, '''Grid Trap''', Ground Zero, Guadalcanal, Guardian 2-Revenge of the only current way mutants, Guerre des galaxies, Guerrero Espacial, GunfighterGalaxia, Game Over I succeed in slowing down enough Timing Instruction - 1st., Gary Linekers s Superstar Soccer, Gauntlet II, Gems Of Stradus, Get Dexter 1 & 0, Go for unlocking Saboteur Gold, Grand Prix, Grand Prix Simulator 2 game., Grand Prix Tennis, Grange Hill, '''Green Beret''', Gregory Loses His Clock, Guardian Angel
Key games here are * '''Gabrielle''': Saboteur 2 Rewind tape* '''Galactic Conqueror''': Rewind tape, idFF (run fine with end of tape)* '''Galactic Games''': "MEM_WR=slowLOADING: Please Wait"* '''Galaxia SPANISH''': crash during play (when crashing on a wall : reboot)* '''Galivan''': black screen* '''Game Over II''': black screen orange border* '''Gauntlet I-The Deeper Dungeon''': nothing displayed* '''Gauntlet III''': welcome image, does freeze with no proposition to change tape side. At end of first tape I insert the second one... Not loading the 3rd tape.* '''Gauntlet''': reboot* '''Gazza II''': "MEM_WR=quickLoading error - Please retry"* '''Gee Bee Air Rally''': return to BASIC* '''Gemini Wings''': black screen pink border, id13 reboot* '''Ghost n Goblins''': Rewind tape* '''Gi Hero''': Searching 00 Loading 00...07 Rewind to 0C (to retry ?) * '''Gilbert-Escape From Drill''': glitch, and Arkanoid II (run fine then black screen* '''Gladiator''': Rewind tape* '''Golden Axe''': reboot id14* '''Golden Basket''': welcome image then reboot.* '''Goliath-Le Defi''': problem during load of welcome image* '''Golpe en la Pequena China''': no key* '''Grand Prix Circuit''': tape stopped with strange id value : 00* '''Grand Prix Master''': blue screen* '''Grand Prix Simulator 1''': idFF (end of tape)* '''Great Courts''': blocked by a password* '''Gremlins-The Adventure''': message "MEM_WR=quickResume a saved game ?"- no keyboard (same in WinAPE), too slow using "MEM_WR=slow"version ripped in 2018 in CPC-Power does run fine.* '''Gremlins 2''': reboot (Turbo Data + Standard Data)- running ok in WinAPE* '''Gryzor''': reboot (Turbo Data + Pure Tone + Sequence of Pulses)* '''Guillzemo Tell''': no keyboard, 4 Turbo Data, last one is big - running ok in WinAPE
[http://www.cpcwiki.eu/forum/programming/cpcHacker 2, Halls of Gold, Happy Letters, '''Happy Numbers''', Happy Writing, Hard Drivin, '''Hard Hat Mack''', '''Harricana-z80-commandsRaid International Motoneige''', Harrier Attack, Haunted Hedges (pacman), Haunted House (txt), Havoc, Hawk Storm version 64K, Heartland, Heathrow International Air Traffic Control, Heavy on the Magick (txt), Helicoptero 2000, Heliot, Helvera-Mistress of the Park (txt), Herberts Dummy Run, Here andThere With the Mr Men, '''Hero''', Hero of the Golden Talisman, Herobotix, Hexenkueche 1 & 2 (Cauldron), Hi-howQ Quiz, Hi Rise, High Moon, '''Highier''', Hijack, '''HMS Cobra''', Hobgoblin (GNG), '''Hold-longUp''', Holdfast, Hollywood Or Bust, Hollywood Palace, Home Runner, '''Hong Kong Phooey''', '''Hot Shot''', House of Usher, How To Be A Hero, Hunchback, '''Hundra''', Hunter Killer, Hustler, Hydrofool, '''Hyperbowl''', Hyperspace 4 (txt)Hacker 1, Hammer-theyHead, Hammer boy, Hercule-take/40/ CPC Z80 Commands and how long they take...]Slayer Of The Damne, Heroes of the Lance,, Hideous, Humphrey, Hunchback 1, Hunchback 2, Huxley Pig, Hypsys
==== Instruction timing * '''Hammerfist''': talk about r005.8white screen blue border, reboot while starting drawing welcome screen id13* '''Handicap Golf''': Rewind tape* '''Hanse''': Rewind tape while loading welcome screen* '''Hardball''': Rewind tape* '''Harvey Headbanger''': id11 id11 '''id12''' id13 - Sequence of pulses of different length - id9C (crash) + Searching 00.16c4 ====Rewind to 0DIn r005* '''HATE-Hostile All Terrain Encounter''': reboot* '''Having Fits Of Madness''': BASIC 1.81 - to retest in 6128 model version.16c3black screen green border.* '''Head Over Heels''': black screen with message "LOADING: Please Wait" id11 id11 '''id12''' (Pure Tone) id13 (crash)* '''Heavy Metal''': reset while loading welcome screen* '''Helichopper''': id19 - Generalized Data Block. Rewind to 03* '''Hero Quest''': black screen, I remark that WAIT_n are badly introduced following plustestmessage "level 12"* '''Heroes of Karn''': "LOADING ERROR" back to BASIC.dsk testbench * '''High Steel''': id11 id11 '''id12''' id13 id70 (WinAPEcrash). I corrected Rewind to 0A* '''Highlander''': message "LOADING: Please Wait" id11 id11 '''id12''' id00 (crash)* '''Highway Encounter''': message "LOADING: Please Wait" id11 id11 id12 id00* '''Histo-Quizz''': Rewind tape (after loading a T80 parameter firing the WRITE action 1 clock before. That unlocks 32 instructions timing in plustest.dsk testbench party) idFF (end of tape)* '''Hive''': id13 id2E (crash).Rewind to 02* '''HKM-Human Killing Machine''': reboot after a count down* '''Hockey''': idFF (end of tape), no keyboard* '''Hopper Copper''': Rewind tape (to retry ?)* '''Hoppin Mad''': Rewind tape (to retry ?)* '''Hostages''': welcome screen and freeze (tape stopped), no keyboard* '''Hot-Rod''': black screen pink border, reboot id14* '''How To Be A Complete Bastard''': white screen, blue border* '''Hudson Hawk''': grey screen, pink border* '''Hunter or Hunted''': Rewind tape* '''Hybrid''': id13 id7F (crash) "Searching 00"* '''Hydra''': black screen border blue* '''Hyper Sports''': welcome screen, and then nothing
In r005.8.16c4i alien, I remark that two WAIT_n are also needed by instructions using 5T during M1 cycle. But in fact the M1 signal is not outputing 4T while 4TIkari Warrior, but cutted at 2T. So that I do here Impossaball, Inca Curse - adventure B (experimentaltxt), I produce a M1 signal output Indigestion, Indoor Soccer, Inertie, Infernal Runner, Inquisitor-Shade of 3T while 5T. Detecting it that way in my WAIT_n generatorSwords, producing then needed Interchange, International Football, '''International Karate Plus''', International Manager, International Rugby, International Tennis, Into Oblivision, Into the Eagle s Nest, '''Invasion of the Zombie Monsters''', Invasores, Invierte y gana (manager), Invitation (txt), ISS-Incredible Shrinking Sphere, IznogoodIlogic All, '''Impossible Mission 1''', Impossible Mission 2 WAIT_n at this moment., Indoor Race, Inside Outing, Invasion, Isoleur, Italian Supercar, Ivan Ironman Stewart s Super Off Road
But plustest.dsk testbench don't pass anymore in r005.8.16c4, testbench show border effect : a correct instruction is marked as bad timing, but in fact it the next one I did modify.
I don* 't know if plustest''i Ball 2 - quest for the Past''': Rewind to 8* '''i Ball''': Rewind to 7* '''Ice Breaker''': reboot* '''Imagination''': Rewind to 7* '''Impossamole''': "LOAD ERROR" level 1.dsk does pass on real AmstradA lot of id14* '''Indiana Jones 3''': black screen during second tape load* '''Indiana Jones 4''': Please rewind* '''Indiana Jones''': counter down : tape stopped in middle of id11 transmission, but it is a really great testbench to progress (without itnoise, r005reboot* '''Infiltrator''': message "LOADING: Please Wait", glitch idFF (end of tape) idem second tape.8.16c4 could * '''Infodroid''': reboot* '''Interdictor Pilot''': game not be realized)running - no key* '''Interieur''': "Rewind tape", end of tape id=FF* '''International 3D Tennis''': 64K version : reboot at begin of welcome image.* '''International Karate''': reset to BASIC* '''International Speedway''': rewind to 15 - great for comparative speed test :)* '''It s a Knockout''': message "LOADING: Please Wait" id14* '''Italia 90 World Cup Soccer''': "WARNING" message, reboot* '''Italy 1990''': game not launched despite of inserting face B
During this workJack and the beanstalk, I remark an instruction that seems badly classified on plustest.dsk : 2A LD HLJack the Nipper II, Jackson City, Jail Break, Jammin, Jet-Boot Jack, Jet, Jet Set Willy-the final frontier (nnpassword needed). This instruction does not use MEM_WR and is not a 5T M1 instruction. So it shall be using 4 NOPs instead , '''JetPac''', Jeux de Kim, Jigsaw Rescue, Jimmy Business, Jimmy s Soccer Manager, Jinks, Jocky Wilson s Compendium of 5 NOPs. LD (nn)Darts, HL does take 5 NOPs '''Jocky Wilson s Darts Challenge''', Joe Blade I, Joe Blade II, Joe Blade III, Johnny Reb II, Jolly Poppa Down (because it does use MEM_WR instructiontxt), as in plustest.dsk testbench here for this instruction.Jolly Roger s Dungeon Escape, Jonah Barringtons Squash, '''Jonny Quest''', Juggernaut, Jump, Jump Jet, Jumper, Jumpman, Jungle Warrior, JustinJack Nicklaus Golf, Jai Alai,
===== Tests on real CPC (by DanyPPC) =====* '''Jack the Nipper I''': game not launched. xFF, still at welcome screen.[http* '''Jackal'''://wwwgrey screen, then reset* '''Jahangir Khan World Championship Squash''': "Tape Loading error.cpcwiki.eu/forum/amstrad-cpc-hardware/need-plustest-dsk-testbench-5-output-on-original-cpc-6128/ CPCWiki."* '''James Clavell s forum Shogun''': Need plustest.dsk testbench 5 output on original CPC 6128]id11 6 times then '''id10'''* '''James Debug dans Le mystère de l'Ile Perdue''': joystick misunderstood* '''Jaws''': id11 4 times then '''id10''' - "Rewind to 04"* '''Jet Bike Simulator''': id13 pure data, pure tone, loop* '''Jet Set Willy II''': Rewind tape (all id11)* '''Johnny Proot II''': Rewind tape (end of tape idFF, all id11)* '''Jungle Jane''': blue screen, idFF (end of tape)* '''Jungle Warfare''': game auto launched, no joystick/keyboard
So 2A is really during 5 NOPs... perhaps MEM_rd has to be slow down with one WAIT_n like for MEM_wr. Perhaps in this case 5TK Y A, '''Kane''', Karl s instruction has not to be slow down. I have to fork r005.8.16c3 to test that. - update : in schematic GateArray does not has "MEM_wr wire" Treasure Hunt, Kart 3000, Kat Trap, Ke Rulen Los Petas (but MEM_req and RDtxt), so can deduce WR'''Kenny Dalglish Soccer Manager''', but in an evil brain's way) - update 2 : all tests failed except one in testbench using this way''Kenny Dalglish Soccer Match''', perhaps because RFSH_n does also use MREQ_n during M1 cycle. Perhaps WAIT_n generator can detect the current OP Code fetched Kentilla (this is conform to [http://www.google.com/patents/US5313621 Patent US5313621 : Programmable wait states generator for a microprocessor and computer system utilizing it ]txt). , Kentucky Racing, Kick off II, '''Killapede''', Killer Cobra, Killer Gorilla, Killer Ring, King Leonard, Klax, Knight Ghost, Knight Lore, Knight Orc, Knight Tyme, Knightmare, Knights and Demons, Kobayashi Maru, Kokotoni Wilf, Kong s Revenge, Krakout, Kung- update : principe of concept validated for one instruction (2A)Fu Master, I can slow down instructions one per one'''Kwik Snax''', I donKYAKarnov, '''Kung-fu'''* '''Kaiser''': Rewind tape* '''Kettle''': reset id11, id13 not reached* '''t know why Kick off I had to insert two WAIT_n instead of one here''': Rewind tape* '''Killed Until Dead Murder At Midnight''': id11, but its results a plustest.dsk testbench with 2A instruction validatedid11, that's done on r005.8.16c5f5 (candidate 5 fork 5id12 id13), but I have several times* '''Kinetik''': "Rewind to revert it to r005.8.16c3f5 I think before going further.03"* '''Knight Force''': Rewind tape* '''Knight Games''': id13* '''Knight Rider''': id13* '''Konami s Golf''': id13* '''Kong Strikes Back''': id13* '''Kotoran s Shadow''': invalid CDT format* '''Kristal''': Rewind tape
About testbench border effectsL'Affaire Sydney (txt), I think that IO_ACKed instructions has to be under same rules L'Affaire Vera Cruz (MEM_wrtxt), modulo 4 etcL'Anneau de Zengara, L Hepiss, La Armadura Sacradda De Antiriad, La Aventura Original (txt) , La Caza del Octubre Rojo, La Chose De Grotemburg (txt), La course a la boussole, La foret Infernale, La France, La Geste D Artillac (txt), La Guerra de las Vajillas (txt), La Trilogie du temple d Apshai, La Ville Infernale, Labyrinth Hall (txt), Langolo del Diavolo, Las Joyas Del Nio, Las Vegas Video Poker, '''Laser''', Laser Blast, Laser Tiempo, Le 5eme Axe, Le Bagne De Nepharia (txt), Le Diamant de l Ile Maudite (txt), Le jeu du Roy, Le Millionnaire, Le spectre d'Anubis (txt), Le Survivant, Le Talisman d Osiris, Le Tour du Monde en 80 jours (txt), Le Tournoi du Siecle, '''Le Tresor de l Amazone''', League Challenge, Legend, Lenguaje, Les aventures du KA- update Menace sur l Arctique, '''Les Diamants de la Peur''', Lettura Rapida, Life Expectancy Zero, Lifeterm (txt), '''Light Force''', Linkword-French, Logiformes, Lop Ears, Lords, Lords of time (txt), Lorna, Los Angeles Swat, Los Pajaros De Bangkok (txt), Los Planetas-El Sistema Solar, Los Templos Sagrados (txt), '''Lost Caves and the Tomb of Doom''', Loto, Lotus Turbo Esprit, Lucky FruitsL Heritage-Panique a Las Vegas, Lee Enfield Space Ace, Little Puff in Dragonland, Lords of Chaos* '''L oeil de Set''': rewind tape* '''La Abadia del crimen''': blue screen and grey border* '''La Malediction de Thaar''': rewind tape idFF* '''La Tour Fantastique''': rewind tape* '''Lala Prologue''': black screen* '''Las Vegas Casino''': Read error B (too quick)* '''Last Duel''': count down, reset* '''Last Ninja 2''': glitch, id14 reboot* '''Le Necromancien''': red screen, blue border* '''Leader Board''': id12 freeze* '''LED Storm''': black screen, rewind at start of block.* '''Lemmings''': no welcome image* '''Les aventures de Jack Buron-big troube in little china''': no keyboard* '''Les Joyaux de Babylone''': "ERREUR CASSETTE"* '''Leviathan''': reset at id14* '''Line of Fire''': inserting second side does nothing* '''Live and Let Die''': black screen idFF (end of tape)* '''Living Daylights''': same result problem than in testbench using this way.dsk version* '''Lords of Midnight''': welcome image, then freeze
==== Instruction timing Mach 4, '''Mach 3''', Macrocosmica, Mad Mix Game, Mad Mix Game 2, Magic Clock, '''Magical Drop CPC''', Manager, Mansion Kali 1 (txt), Mansion Kali 2 (txt), Mantis 1 (txt), Mantis 2 (txt), Mapa del Cielo, Master Chess, Match Point, Mathasard, Mathe Stunde 1, Max, Meltdown, Mercenaire, Mexico 86, Minas, Misil Atack, Missile Ground Zero, Missiles, Molecule Man, Money Molch, Monster of Murdac, Monty Mutant, '''Monument''', Mordon s Quest (txt)Mariano The Dragon In Capers In Cityland, Marius Tresor Foot, Masters of the Universe, Mathex n1, Maziacs, Megacorp, Meganova, Message from Andromada (txt), Miami Cobra GT, Microprose Soccer* '''M enfin''': talk about r005.8.16c20 ====sound freeze during welcome pictureInstruction timing seems all respected following plustest* '''Mahjong''': Rewind tape* '''Manic Miner''': crash after loosing one time.dsk, but I think it isn* 't enough''Mansion''': Rewind tape during first mission* '''Marble Madness-Deluxe Edition''': blue screen* '''Marsport''': password* '''Master of the lamps''': Rewind tape* '''Matchday 2''': black screen blue border* '''Mercenary Escape from Targ''': welcome screen, so itno keyboard* 's still ''Mercs''': reboot* '''Metropol''': back to basic at first round of play* '''Miami Vice''':* '''Michel Futbol Master Super Skills''': reboot* '''Mickey Mouse''': reboot* '''Micro Sapien''': Rewind tape* '''Mike Head S Computer Pop Quiz''': menu without keys* '''Mineur''': Read error a candidate version.* '''Mobile Man''': reboot* '''Monopoly''': grey screen* '''Montsegur''': reboot* '''Moonblaster''': game not launched
Even prefixed and double prefixed instructions are taken into account by my WAIT_n generator.
WAIT_n generator is finally juste inserting a certain number of WAIT_n following executed instruction + a mod 4. In forum if I remembered, you don't do the next mod 4 alignement after a recepted IO_ACK (have to check that)
I try on this version to get an intelligent IO_ACK* * '''Breaking Baud.cdt''': in JavaCPC no pause, last part "pink floral" heart is missing. As explain at begin of demo, instructions just has a fixed time (array are executed during they are written in memory, speed of instruction timing) and IO_ACK does not influence on themtape against speed of Z80.. So IO_ACK perhaps has to remove one WAIT_n inserted by GateArray.
I have regressions on this ===On ZX-Uno FPGAmstrad version, Still Rising===Games that doesn's scroll, t run are :* '''adios_a_la_casta.dsk''': bad sound. Does pass hacking memory banks this way : else b"1100" when RAMbank="100" and Trail Blazer palette offset at left(A(15)='0' and A(14)='1') else b"1101" when RAMbank="101" and (A(15)='0' and A(14)='1') else b"1110" when RAMbank="110" and (A(15)='0' and A(14)='1') else b"1111" when RAMbank="111" and (A(15)='0' and A(14)='1') else b"10" & A(15 downto 14); -- default value* '''Ghouls'n'Ghost.dsk''': black screen during game. RAM is not relaxed enought to permit changing address just after knowing if Z80 does a read or a write (ROM written=> does write on RAM hidden behind)
"RET cc" instruction seems not respecting original timing in T80* '''jdva6. I had 2 clocks in last TStates of itdsk''': no keyboard... [https://github.com/renaudhelias/RubikCubePaletteCPC/tree/master/JDVA%236_test JDVA#6 test]
I don't understand why I have to add 2 WAIT_n when 1 WAIT_n seems suffisant, I think there is some problem around my Antonio Villena mail "PLEASE_WAITZXDOS conversion of your CPC core" component (hack of T802019/01/29 Hi Renaud It's WAIT_n entry), perhaps finally T80for asking if you plan a conversion of your CPC core for this platform. It's WAIT_n entry is finelike ZX-Uno, as finally I just insert a certain number but with: -A bigger FPGA, LX16 instead LX9. -18 bit DAC -32Mb of WAIT_n during second clock of M1SDRAM, MEM_wr slow is unvalidated : Gatearray also 512K of Amstrad doesn't have SRAM -dual joystick port -Separate PS/2 joystick and mouse If you are interested I can provide the needed "WR" wiretwo addon boards, soyou only need the LX16 board. Bought from Aliexpress is about 18 EUR. https://es.aliexpress.com/store/product//606998_32818384452.html Regards
Next step shall be destroying "PLEASE_WAIT" component I think== Effort done ===== VGA ===Pixels and VRAM. Palette and rasters. CRTC0==== VGA: CRTC0 ====CRTC0 seems the best one, in order some demo does cry when detecting a poor CRTC1 (CRTC1 seem a low cost version of CRTC0). I have to add 1 WAIT_n and not 2 with implement a CRTC0 instead of my WAIT_n generatorcurrent CRTC1...
T80 WAIT_n has also to be checked, I know that inserting a WAIT_n seems generating a seconde IO_ACK edge during an IO_ACKIn fact CRTC1 is the best one. CRTC2 is the low cost version. CRTC0 did appears before CRTC1.
Have to check also the moment IO_ACK is taken into account during M1 signal (I think it's at begin of it, but have to re-check that)Some demos are running only on CRTC0 and others CRTC1.
===== RET cc and WAIT_n timing analysis =====Normaly, without WAIT_n generator (even modulo 4), NOP should take 1 M-cycles and 4 T-states, so this instruction should pass using plustestDone in r005.dsk at 0x008.14. Detected as CRTC0 by WakeUp! - "Enjoy the show" message displayed. Does fail here (my approach is incorrect)
In r005.6, cpctest8.dsk did pass15. Removing MEM_wr:slow both tests does still run fine WakeUp! (NOPCRTC0/HALT (x00 x76MEM_wr quick)). Removing full mod4 WAIT_n generatordetected as Emu first time, cpctest.dsk and plustest.dsk after a quick reset, does failsay detected as CRTC0. So NOP has to be synchronized ? (plustest.dsk is full of NOPs)
My WAIT_n generator currently passing fully plustest.dsk's testbench is using the bad edgeIn ZX-Uno FPGAmstrad, something is wrong, it's a false positive. I know that NOP, HALT and IO_ACK/INT has to be good for this test to be validimplemented CRTC0. It's not the case here, so in fact my table of latencies is not the good one : running, but corrections are done on several bad instructions, some of them are even illogical, as this "RET cc" instruction where I had to hack the Z80 itself to reach a passing test, so something is wrong, and that thing is firstly the current WAIT_n generator clock edge (in comparison againts Z80's clock edge)
Have to change my approach, perhaps using invariant CRTC1 has double sized VSYNC against CRTC0 (table of full instruction chrono versus reality), validate instruction timing before trying validating IO_ACK interrupts. Write one table from plustest.dsk's testbench launched on WinAPE, and another table from original Z80 documentation, and deduce a first theorical candidate table of latencies. I have to trust first in my instruction timing tables (and have to write them both completely...moustache test)
Prefixed instruction seems having only one M1 ==== VGA: Z80 doc show that a prefixed instruction take 4T more time. But last time plustest.dsk did pass thinking prefixed instruction are totally separated (M1 for DD, M1 for CB, M1 for "RLC (IX+D)"), so each prefix has its own M1, and following instruction has also its own M1VRAM ====ram_palette.
Is IO_ACK itself a separated instruction ? I think notVRAM contains 800x300 amstrad pixels (VZoom x2), it's more about a hack of a current instruction, adding two autowait displayed VGA 800x600@72Hz with fix regular border at 768×576 and making its business during this inserted timesfix inside border at 768×544.
IO_ACK offset into INT In ZX-Uno, VRAM contains 800x300 amstrad pixels (interruptVZoom x2) should not implicated by WAIT_n generator, and it seems that a WAIT_n during T2 is ignored because of autowait already inserted at this moment... for synchronizing an IO_ACK, I have normaly to insert WAIT_n during T2+2. No way, instruction itself is synchronized, so IO_ACK is synchronized alsodisplayed 640x480@60Hz, you don't have to insert WAIT_n during T2+2with vertical only border.
http* simple_GateArrayInterrupt.vhd (GA to VRAM) parameters :VRAM_Hoffset//wwwVRAM_Voffset* aZRaEL_vram2vgaAmstradMiaow.cpcwiki.euvhd (VRAM to VGA) parameters : H_BEGIN/forumH_END/emulators/cpc-z80-timingV_BEGIN/ V_END (theorical fixed values)To calibrate : ~ a WAIT_n VRAM_Hoffset++ does not use RAM access, so offset one char left. VRAM_Voffset++ does offset one line up. On display H_BEGIN does begin to scan lines of VRAM. But V_BEGIN does not slow down a "CPC instruction" (hypothesis) - but what about an IO_ACK during NOP enter in this case ?consideration here : vertical=0 does begin to scan columns of VRAM.
In docoriginal CPC, IO_ACK begin after T2, during the two autowait insertedtop border has 1/2 char more than bottom border. I used Batman Forever default welcome/calibration screen to calibrate VRAM offsets. So no way On ZX-Uno I used Arkanoid to detect that an instruction is IO_WAITing before slowing it following "slow down" instruction timing tablecalibrate VRAM offsets.
http://www.cpcwiki.eu/forum/programming/cpc-z80-commands-RAM_palette contains the ink list and-how-long-they-take/30/ So, it's more correct to not think the mode for each line of it stretching the M cycleVRAM, but instead not starting the next one that requires a memory access until the 4th cycle. If you think sampled at horizontal middle of it like this800x600 screen, it also explains the weird exception that happens for interrupt handling. Normally, responding to an interrupt adds 1us on the CPC. That's because it actually just adds 2 T states for the interrupt acknowledge before the next instruction fetch. However, in case where the last M cycle takes 6 T states, the interrupt acknowledge doesn't delay the instruction prefetch and so the usual 1us delay doesn't occurused at begin of each line. "Simples!" - ralferoo(4T equals 1us equals 1 NOP => modulo 4 synchronization of M1)
So you slow down instructions following a slowing down instruction table, slowing it the less you can, and then IO_ACK comes or not, and then you synchronize next M1 putting WAIT_n during T2 modulo 4. IO_ACK two autowaits are not prolongated.==== VGA: TODO : arnoldemu testbench ===='''arnoldemu testbench: crtctest'''
ralferro explains also that stretching instruction timing depends Adding choice of memory used CRTC 0 or not by instruction. I know that Amstrad schematics does not use the MEM_WR wire. So it could be hard to deduce if they added 1 or more WAIT_n for certain instructions. But I'm more about 1 WAIT_n inserted at maximum each time (it's more easy to hard implements)on OSD, and the modulo 4 synchro, let's see results of my current experiment (comparing time instruction of Z80 and plustest.dsk testbench, deducing diff table of "slowing down instructions") wippassing this test could be great.
==== Instruction timing VGA: talk about r005.8.16c29 TODO : winape testbench ====This version does implements correctly a theorical WAIT_n generator '''winape testbench: I used a script comparing Z80 doc timings to plustest.dsk testbench result on real CPC, I deduce that inserting each time 2 WAIT_n does the stuff (that will my first approach), I saw also that first set of instruction timing is fully covered by Z80 doc, so plustest.dsk testbench failing on this part is not due to table slowing down instruction timing (WAIT_n generator's table of slowing down instruction timing), this isntructioon have to be slowed somewhere else : perhaps a bug inside Z80 itself or else the equation NOP/HALT/ACK to review, instructions concerned here seems all about "JUMP" except two instruction (a LD and an EX), in past I did already tested Z80 instruction timing themself and found no problem this way.''
I also revisited the edges of WAIT_n generator, to insert WAIT_n at 2T.a better border heuristic
I also removed the edge detection of IO_ACK on gatearrayUsing winape testbench (plustest), replacing it by state detection test 2 does show somes problems while border does go out of IO_ACKscreen, resulting cpctest's testbench back : this test of HSYNC width is now successfullnegative border does hide line itself.
plustest.dsk has some "missing tests" but in fact there are the prefixes : CB, DD, ED, FD, used to launch other areas of instructions=== bootloader ===SDCARD and RAM.
HALT is the only one instruction that will be always OK on plustest.dsk instruction timing testbench. As this instruction cannot be timed.(nothing to say here, really ???)
Megablasters seems running fine on r005.8.16c29. Using 4 disk version of Megablasters (old one), sometimes bombs doesn't explode, it's normal : in this case you have to press the second fire button (gameplay...)=== GA ===
plustest.dsk source code ==== GA: alignment of HSYNC Interrupt ====Interrupt are available on winape websiterespected since version "candidate 001" of FPGAmstrad, I have to explore themMarkus does help me a lot about it.
{| class="wikitable"|-! Hex !! Inst !! CPC timing !! r005[[File:JavaCPC_running_norecess.8.16c29|-| 32 || LD (nn),A || 4|| 3|-| 3A || LD A,(nn) || 4 || 3|-| C0 || RET NZ || 2/4 || 2/3|-| C4 || CALL NZ,nn || 3/5 || 3/4|-| C5 || PUSH BC || 4 || 3|-| C7 || RST 0H || 4 || 3|-| C8 || RET Z || 4/2 || 3/2|-| CC || CALL Z,nn || 5/3 || 4/3|-| CD || CALL nn || 5 || 4|-| CF || RST 8H || 4 || 3|-| D0 || RET NC || 2/4 || 2/3|-| D4 || CALL NC,nn || 3/5 || 3/4|-| D5 || PUSH DE || 4 || 3|-| D7 || RST 10H || 4 || 3|-| D8 || RET C || 4/2 || 3/2|-| DC || CALL C,nn || 5/3 || 4/3|-| DF || RST 18H || 4 || 3|-| E0 || RET PO || 2/4 || 2/3|-| E3 || EX (SP),HL || 6 || 5|-| E4 || CALL PO,nn || 3/5 || 3/4|-| E5 || PUSH HL || 4 || 3|-| E7 || RST 20H || 4 || 3|-| E8 || RET PE || 4/2 || 3/2|-| EC || CALL PE,nn || 5/3 || 4/3|-| EF || RST 28H || 4 || 3|-| F0 || RET P || 2/4 || 2/3|-| F4 || CALL P,nn || 3/5 || 3/4|-| F5 || PUSH AF || 4 || 3|-| F7 || RST 30H || 4 || 3|-| F8 || RET M || 4/2 || 3/2|-| FC || CALL M,nn || 5/3 || 4/3|-| FF || RST 38H || 4 || 3|}jpg]]
=== Test of a real Zilog 80 ===JavaCPC running norecess's "using-interrupts" code [[Filehttp:Z80fx2bb//norecess.jpgcpcscene.net/using-interrupts.html]]Code name : Z80fx2bb, real Z80@2MHz (instead of 4MHz) on fx2bb extension card.
[[http://wwwIt could be interesting to test this asm code on next version of FPGAmstrad.youtube.com/watch?v=YYnvkR5v3D0 http://www.youtube.com/watch?v=YYnvkR5v3D0]]
For it I plug all wires simply from 1 to 40. Some wires are cut, some are Vcc, others GND. Z80 output are directly connected, Z80 input are pull-up with red-red-red resistors (I like red), Z80 is powered 5v (pmod can give 5v using jumper). In fact z80 is so old component that powering it 5v does output 3.3v==== GA: Sniffing of a real Amstrad ====[[File: cpc_plus_m1.jpg]]Code name: Raptor
In fact the only difference between [[T80]] I listen to some wires of opencore and real Z80 is that [[T80]] runs on rising_edgemy Amstrad CPC 6128 plus, and Z80 runs during low state. Test past with little modification but I can't access VSYNC/HSYNC output of sequencer forcing it CRTC, so I have to buy another model in order to do nothing during low state this test. In fact you can listen at clock of z80Amstrad and transmit it to FPGA DCM component, resulting a downclock (memory is too overclocked accelerated clock sequence, that's it, with this sequencer modification)FPGA DCM you can overclock output Amstrad clock signal in order to insert more operations, perhaps using buffer on address bus and data bus could solve I use this detailtip for listening signals and save them inside starter kit asynchronous RAM (write, stop write, write, stop write... but as it runs for me it is not I’m a problemperfectionist paranoid...)
==== TODO : Z80 testbench ====You can power Amstrad CPC using extension port, applying 5v. By doing it, power down button of Amstrad doesn’t run. Using this way you reach a common 5v power between starter-kit and Amstrad. I connected wires from extension port directly to FPGA, as they are used just for listening.
[http==== GA://www.cpcWAIT_n generator -powercurrently in r008.com/index5.php?page14 =detail&num=12883 CPC-Power Z80 FULL TEST (UK) (2012) - UTILITAIRE]==Instruction timing.
Some errors detected I tested instruction timing of [[T80]] compare to instruction timing of JavaCPC emulator. I deduce synchronization of Z80 with CRTC on M1 signal by WAIT_n insertion in r005order to have a multiple of 4 Tstates per instruction.8.4 I deduce also one WAIT_n inserted during MEM_WR operation (test done by Philippe D.yes I log testbench [[T80]], I’m crazy)
I just made a test bench log of [http://www.winape[T80]] (log of instruction's M1, and first M1 coming after knowing that I send a lot of NOP after my instruction), and compare it to a JavaCPC timing array.net/download/plustest.zip WinAPE plustest.zip Some instructions was not tested (including Instruction interrupt wait, and Interrupt special timing (instructions with change timing tests)]), but all others passed correctly.
===== Z80 architecture =========== a) T80.vhdl ======17 pages of source codes MEM_WR has an OSD menu choice to readswitch between "quick" and "slow", "slow" mode does insert ONE WAIT_n during detection of MEM_WR. This switch exists because somes games are running in "slow" mode and others in "quick" mode.
Not analyzed yet completlyAn elegant fork by Sorgelig, sum up nicely the "MEM_WR:slow" algorithm + the HACK_Z80 flag of r008.5.14 : T80pa CPU ( (...) .cen_p(ce_4p & (WAIT_n | no_wait)), .wait_n(1) // (cyc1MHz | (IORQ_n & MREQ_n) | no_wait) ); // Current WAIT_n generation is not correct! // It should use WAIT_n instead (see commented out code above ^^) reg WAIT_n; wire acc = (MREQ_n | ~RFSH_n) & IORQ_n; always @(posedge clk) begin reg old_acc; if(ce_4p) begin old_acc <= acc; if(old_acc & ~acc) WAIT_n <= 0; if(cyc1MHz) WAIT_n <= 1; end end
Contains the main workflow of Z80==== GA: current MCycle and its current TStateWAIT_n generator - talk about r008.5.14 ====
Contains T80_ALU.vhdl In fact it exists several instruction making MEM_wr, and T80_MCode.vhdl componentsadding each one ONE WAIT_n does result in different case of synchronization.
====== b) T80_ALU[http://www.vhdl ======6 pages of source codes to readcpcwiki.eu/forum/emulators/cpc-z80-timing/ CPC Z80 timing]
Not analyzed yet completly. This analyse can certainly be wrong : wipIf it's about managing GA reading pixels, perhaps not only M1 signal are synchronized but also the MEM_RD and MEM_WR accesses at another offset.
Contains flags [http: C N P X H Y Z S C : carry - set if result did not fit in the register N : negative//amstrad.eu/modules/newbb/viewtopic.php? - last instruction was substract P : parity or overflow - overflow example : signed, 7F+7Fpost_id=FE with overflow setted X : undocumented H : half carry - set if 4bit first bits of result did not fit in the register Y : undocumented Z : zero - set if result is zero S : sign - it is an input ?Contains ALU_Op : [ADD ADC SUB SBC AND XOR OR CP] ROT BIT [SET RES24592 Timings instructions Z80 sur CPC] DAA
ALU_Op is the basic instructions of Z80 coded here. T80_ALU.vhdl If interruption r52 is regular, even while making a slavecontinues MEM_WR, a service exposed to T80_MCode.vhdl throw T80.vhdlinterruption (int<='1') shall be taken into account above WAIT_n insertions ?
[[http://www.z80.info/decoding.htm § Disassembly tables]] shall make a cool ALU_Op quick reference cardIn Z80 sequence diagram, doesn't it ?an IO_ACK(+M1) is preceded by M1 (single)
====== c) T80_MCodecpctest.vhdl dsk -Timing Instruction- is different while using mode "MEM_WR=slow" and "MEM_WR=====First 5 pages, and last 2 pages of source codes to readquick". Others pages are Strangly better using "always the sameMEM_WR=quick" architectually speaking.
Not analyzed yet completlyCurrent version is using "Z80_HACK=true" (parameter set during compilation), that shunt Z80. This analyse can certainly be wrong : wipWAIT_n entry, Z80.clock is slow down during theses WAIT_n. It's the only current way I succeed in slowing down enough Timing Instruction for unlocking Saboteur 2 game.
Gives instructions lengh Key games here are : MCycles, TStates Saboteur 2 (please remark the 's' at end of theses words...)run fine with "MEM_WR=slow", in [[http://www.zilog.com/docs/z80/um0080.pdf Z80 doc]] each instruction is timing described using does freeze with "M CyclesMEM_WR=quick" ) and Arkanoid II (run fine with "T StatesMEM_WR=quick" vocabulary., too slow using "MEM_WR=slow")
It's a "controler" (proof [http: you have some Set_*_To outputs), does gives orders to T80_ALU//www.vhdl throw T80cpcwiki.vhdleu/forum/programming/cpc-z80-commands-and-how-long-they-take/40/ CPC Z80 Commands and how long they take...]
Actions of this controler are ==== GA:* ALU_Op : the action !* I_DJNZ I_CPL I_CCF I_SCF I_RETN I_BT I_BC I_BTR I_RLD I_RRD I_INRC : actions not for ALU WAIT_n generator - plustest-5 - Tests on real CPC (wiring input/ouput, changing flags...by DanyPPC)====* Save_ALU[http:/PreserveC : an option about register "erased or not" at next instructionInstructions not coded in T80_MCode/www.vhdl but in T80cpcwiki.vhdl (strange, barbarian part of code ?) :* Jumpeu/Eforum/XY Call RstP LDZ LDW LDSPHL Special_LD ExchangeDHamstrad-cpc-hardware/Dpneed-plustest-dsk-testbench-5-output-on-original-cpc-6128/AF/RSCPCWiki's forum : Need plustest.dsk testbench 5 output on original CPC 6128]
Inc_WZ register So 2A is really during 5 NOPs... perhaps MEM_rd has to be slow down with one WAIT_n like for MEM_wr. Perhaps in this case 5T's instruction has not to be slow down. I have to fork r005.8.16c3 to test that. - update : take a look at [in schematic GateArray does not has "MEM_wr wire" (but MEM_req and RD, so can deduce WR, but in an evil brain's way) - update 2 : all tests failed except one in testbench using this way, perhaps because RFSH_n does also use MREQ_n during M1 cycle. Perhaps WAIT_n generator can detect the current OP Code fetched (this is conform to [http://www.rightogoogle.com/2014patents/10/how-z80s-registers-are-implementedUS5313621 Patent US5313621 : Programmable wait states generator for a microprocessor and computer system utilizing it ]). -update : principe of concept validated for one instruction (2A), I can slow downinstructions one per one, I don't know why I had to insert two WAIT_n instead of one here, but its results a plustest.html § The WZ temporary registers]. Itdsk testbench with 2A instruction validated, that's a tmp internal register in factdone on r005.8.16c5f5 (candidate 5 fork 5), but I have to revert it to r005.8.16c3f5 I think before going further.
===== Some bad instruction timing analysis =====Based on [[http://www.winape.net/ WinAPE>download>Plus test>plustest.dsk]] About testbenchborder effects, mapped using [[http://clrhome.org/table/ Z80 instruction set - ClrHome]], instruction described then in [[http://www.zilog.com/docs/z80/um0080.pdf Z80 doc]], against [[http://www.winape.net/ WinAPE]] passing testbench timing.{| class="wikitable"|-! Hex !! Inst !! CPC timing !! MEM_wr:quick !! MEM_wr:slow !! remark|-| 02 || LD I think that IO_ACKed instructions has to be under same rules (BC), A || 2 || || 3 || Fixed on r005.8.16c3|-| 10 || DJNZ, e || 4/3 || 4/2 || 4/2 || T States begin by "(5, " : M1 is longer than 4.Seems adding also one Wait_n in this case (as about MEM_wr)|-| 12 || LD (DE), A || 2 || || 3 || Fixed on r005.8.16c3|-| 22 || LD (nn), HL || 5 || modulo 4 || 6 || Fixed on r005.8.16c3|-| 2A || LD HL, (nnetc) || 5 || 4 || 4 || MEM_WR not used by here,it seems correct following doc : 4+3+3+3+3=16, 16/4=4.Damn.|-| 32 || LD (nn), A || 4 || || 5 || Fixed on r005.8.16c3|-| 34 || INC (HL) || 3 || || 4 || Fixed on r005.8.16c3|-| 35 || || 3 || || 4 || Fixed on r005.8.16c3|-| 36 || || 3 || || 4 || Fixed on r005.8.16c3|-| 70 || || 2 || || 3 || Fixed on r005.8.16c3|-| 71 || || 2 || || 3 || Fixed on r005.8.16c3|-| 72 || || 2 || || 3 || Fixed on r005.8.16c3|-| 73 || || 2 || || 3 || Fixed on r005.8.16c3|-| 74 || || 2 || || 3 || Fixed on r005.8.16c3|-| 75 || || 2 || || 3 || Fixed on r005.8.16c3|-| 77 || || 2 || || 3 || Fixed on r005.8.16c3|-| C0 || RET nz || 2/4 || 2/3 || 2/3 || RET cc, inverse of RET z.|-| C4 || || 3/5 || || 3/6 || Fixed on r005.8.16c3|-| C5 || PUSH bc || 4 || 3 || || PUSH qq (same as F5), ok using MEM_wrupdate :low|-| C7 || RST 00h || 4 || 3 || 3 || RST p. Fixed on r005.8.16c3. T States begin by "(5, " : M1 is longer than 4.|-| C8 || RET z || 4/2 || 3/2 || 3/2 || RET cc, it seems correct following doc: true@5+3+3=>3*4; false@5=>2*4.T States begin by "(5, " : M1 is longer than 4.|-| CC || || 5/3 || 5/3 || 6/3 || Fixed on r005.8.16c3|-| CD || || 5 || || 6 || Fixed on r005.8.16c3|-| CF || RST 08h || 4 || 3 || 3 || RST p. Fixed on r005.8.16c3|-| D0 || RET nc || 2/4 || 2/3 || 2/3 || RET cc, inverse of RET c.|-| D4 || || 3/5 || || 3/6 || Fixed on r005.8.16c3|-| D5|| PUSH de || 4 || 3 || || PUSH qq (same as F5), ok result in testbench using MEM_wr:low|-| D7 || RST 10h || 4 || 3 || 3 || RST pthis way. Fixed on r005.8.16c3|-| D8 || RET c || 4/2 || 3/2 || 3/2 || RET cc|-| DC || || 5/3 || || 6/3 || Fixed on r005.8.16c3|-| DF || RST 18h || 4 || 3 || 3 || RST p. Fixed on r005.8.16c3|-| E0 || RET po || 2/4 || 2/3 || 2/3 || RET cc, inverse of RET pe.|-| E3 || || 6 || 5 || 6 || Fixed on r005.8.16c3|-| E4 || || 3/5 || || 3/6 || Fixed on r005.8.16c3|-| E5 || PUSH hl || 4 || 3 || PUSH qq (same as F5), ok using MEM_wr:low|-| E7 || RST 20h || 4 || 3 || 3 || RST p. Fixed on r005.8.16c3|-| E8 || RET pe || 4/2 || 3/2 || 3/2 || RET cc|-| EC || || 5/3 || || 6/3 || Fixed on r005.8.16c3|-| EF || RST 28h || 4 || 3 || 3 || RST p. Fixed on r005.8.16c3|-| F0 || RET p || 2/4 || 2/3 || 2/3 || RET cc, inverse of RET m.|-| F4 || || 3/5 || || 3/6 || Fixed on r005.8.16c3|-| F5 || PUSH af || 4 || 3 || || PUSH qq, 5+3+3=11<3*4, is MEM_WR prologation effective two times here 1T+1T?yes: pushing a register pair here, ok using MEM_wr:low|-| F7 || RST 30h || 4 || 3 || 3 || RST p. Fixed on r005.8.16c3|-| F8 || RET m || 4/2 || 3/2 || 3/2 || RET cc|-| FC || || 5/3 || || 6/3 || Fixed on r005.8.16c3|-| FF || RST 38h || 4 || 3 || 3 || RST p. Fixed on r005.8.16c3.|-|}
CC codes ==== GA: all okWAIT_n generator - plustest-9 - Tests on real CPC (by GUNHED and Kris) ==== DD codes [http: somes ko ED codes : somes ko FD codes : somes ko DD CB codes : all ko FD CB codes //www.cpcwiki.eu/forum/amstrad-cpc-hardware/need-plustest-dsk-testbench-9-output-on-original-cpc-6128/ CPCWiki's forum : all koNeed plustest.dsk testbench 9 output on original CPC 6128]
r005.8.16c4 GUNHED results :[[File System 1:FPGAmstrad plustest5 r005CPC6128, CRTC2: Test 9 works normal until the &EC codes, there are two errors marked with an "X".8 &ED, &46: 2 &ED, &4E: 2 After &ED, &5D it suddenly stops working! System 2: 6128 Plus: &ED, &46: 2 &ED, &48 5 &ED, &49: 5 &ED, &4E: 2 &ED, &50: 5 &ED, &51: 5 &ED, &58: 5 &ED, &59: 5 After &ED, &5D it suddenly stops working! Probably a crash, since a spot appears on screen.16c4 part1Kris results : Here are my results (teste performed on CPC 6128 CRTC 1) Pictures of each screen attached in the .png|thumbnail|FPGAmstrad_plustest5_r005rar file.8.16c4_part1]][[File:FPGAmstrad plustest5 r005 (.8.16c4 part2.png|thumbnail|FPGAmstrad_plustest5_r005)In pictures of Kris, after ED5D, it does stop also.8Only ED test part has some failings :* ED46:C* ED4E:CIn WinAPE (by default CPC 6128 CRTC1), ED test does finish its screeen result, with several fails :* ED46:2* ED4E:2* ED66:2* ED6E:2Others screens results after does pass. Relaunching once again in WinAPE, same results.16c4_part2]]
r005.8.16c6 results ==== GA:WAIT_n generator - RET cc and WAIT_n timing analysis ====[[File:FPGAmstrad plustest5 r005.8.16c6 part1.png|thumbnail|FPGAmstrad_plustest5_r005.8.16c6_part1]][[File:FPGAmstrad plustest5 r005IO_ACK offset into INT (interrupt) should not implicated by WAIT_n generator, and it seems that a WAIT_n during T2 is ignored because of autowait already inserted at this moment.8.16c6 part2.png|thumbnail|FPGAmstrad_plustest5_r005for synchronizing an IO_ACK, I have normaly to insert WAIT_n during T2+2.8No way, instruction itself is synchronized, so IO_ACK is synchronized also, you don't have to insert WAIT_n during T2+2.16c6_part2]]
===== Some bad instruction analysis =====Based on [[httpshttp://cpcrulezwww.frcpcwiki.eu/applications_CPMforum/emulators/cpc-utilz80-zexall.htm Zexalltiming/ : Z80 ~ a WAIT_n does not use RAM access, so does not slow down a "CPC instruction set exerciser]], running fine in JavaCPC.====== ED A9 cpd" (rhypothesis) / ED A1 cpi(r) ======Problem here : CPDR and CPIR has same implementation than CPD and CPI.- but what about an IO_ACK during NOP in this case ?
=== Alignment of HSYNC Interrupt ===Interrupt are respected since version In doc, IO_ACK begin after T2, during the two autowait inserted. So no way to detect that an instruction is IO_WAITing before slowing it following "candidate 001slow down" of FPGAmstradinstruction timing table.
[[Filehttp:JavaCPC_running_norecess//www.jpg]]cpcwiki.eu/forum/programming/cpc-z80-commands-and-how-long-they-take/30/ So, it's more correct to not think of it stretching the M cycle, but instead not starting the next one that requires a memory access until the 4th cycle. If you think of it like this, it also explains the weird exception that happens for interrupt handling. Normally, responding to an interrupt adds 1us on the CPC. That's because it actually just adds 2 T states for the interrupt acknowledge before the next instruction fetch. However, in case where the last M cycle takes 6 T states, the interrupt acknowledge doesn't delay the instruction prefetch and so the usual 1us delay doesn't occur. "Simples!" - ralferoo(4T equals 1us equals 1 NOP => modulo 4 synchronization of M1)
JavaCPC running norecess's "using-interrupts" code [[http://norecessSo you slow down instructions following a slowing down instruction table, slowing it the less you can, and then IO_ACK comes or not, and then you synchronize next M1 putting WAIT_n during T2 modulo 4.cpcsceneIO_ACK two autowaits are not prolongated.net/using-interrupts.html]]
It ralferro explains also that stretching instruction timing depends of memory used or not by instruction. I know that Amstrad schematics does not use the MEM_WR wire. So it could be interesting hard to test this asm code on next version deduce if they added 1 or more WAIT_n for certain instructions. But I'm more about 1 WAIT_n inserted at maximum each time (it's more easy to hard implements), and the modulo 4 synchro, let's see results of FPGAmstradmy current experiment (comparing time instruction of Z80 and plustest.==== TODO : arnoldemu dsk testbench - cpctest ====[http://www.cpcwiki.eu/forum/emulators/amstrad-cpc-%27acid%27-test/ forum : amstrad cpc , deducing diff table of "acidslowing down instructions" test] => ''I have uploaded updated tests : [http://cpctech.cpc-live.com/test.zip http://cpctech.cpc-live.com/test.zip]'')
Tests done here ==== GA: ppi/psg/cpctestWAIT_n generator - talk about r005.8.16 ====OSD menu has now "WAIT_n:slow|quick", a WAIT_n generator is implemented adding 0, 1 or 2 WAIT_n per instruction.
[[File:arnoldemu_testbench_CPCTESTI revisited the edges of WAIT_n generator, to insert WAIT_n at 2T (like explain in Z80 doc), so normaly it is retro-compatible with official T80. Doing this way I can set HACK_Z80 flag at false (T80.WAIT_n is now used in r005-6.png]]8.16)
In r005.6, I reach successfully some arnoldemu tests to calibrate more efficiently HSYNC interrupt : ppi.binalso removed the edge detection of IO_ACK on gatearray, psg.binreplacing it by state detection of IO_ACK, resulting cpctest.bin's testbench back : this test of HSYNC width is now successfull.
Games unlocked by r005plustest.6 dsk has some "missing tests" but in fact there are the prefixes : Sigma7CB, Pac-landDD, Golden TailED, FD, used to launch other areas of instructions.
In r005.8, Prehistorik HALT is running finethe only one instruction that will be always OK on plustest.dsk instruction timing testbench. As this instruction cannot be timed.
In plustest.dsk testbench 5 does pass, except for two instruction : CPIR and CPDR - btw, in r005.8.416, arnoldemu testbench its instructions are using then same "cpctestWAIT_n generator" does fail :slower than CPI/CPD : none (no WAIT_n added for theses instructions)
In r005==== GA: WAIT_n generator - plustest.8asm ====About 22 pages of source code using 3 columns per page.7 .stdinst (launch tests on several list of instruction, arnoldemu testbench "cpctest" is OKsome instructions are tested differently using test functions : normtest, testit (testdjnz), rsttest...)
In r005.8.14 version ld a, using default mode "MEM_wr:quick", is OK. And Prehistorik II is running fine.#c7 call rsttest => C7 RST 0H 4 3
ld a,#cf call rsttest ===== TODO : arnoldemu testbench - crtctest =====> CF RST 8H 4 3Adding choice of CRTC 0 or 1 on OSDrsttest seems a nice candidate to explore, and passing this test could be greatas all its tests are failing here.
=== ram_palette === .times1VRAM contains 800x300 amstrad pixels (VZoom x2CPC Timing array (first instruction set)), displayed VGA 800x600@72Hz with fix regular border at 768×576 and fix inside border at 768×544.
* simple_GateArrayInterrupt.vhd (==== GA to VRAM) parameters : VRAM_Hoffset/VRAM_Voffset* aZRaEL_vram2vgaAmstradMiaow.vhd (VRAM to VGA) parameters TODO : H_BEGIN/H_END/V_BEGIN/V_END (theorical fixed values)arnoldemu testbench ====To calibrate '''arnoldemu testbench: VRAM_Hoffset++ does offset one char left. VRAM_Voffset++ does offset one line up. On display H_BEGIN does begin to scan lines of VRAM. But V_BEGIN does not enter in consideration here : vertical=0 does begin to scan columns of VRAM.cpctest'''
In original CPC, top border has 1[http:/2 char more than bottom border/www. cpcwiki.eu/forum/emulators/amstrad-cpc-%27acid%27-test/ forum : amstrad cpc "acid" test] => ''I used Batman Forever default welcomehave uploaded updated tests : [http://cpctech.cpc-live.com/test.zip http://cpctech.cpc-live.com/calibration screen to calibrate VRAM offsetstest.zip]''
RAM_palette contains the ink list and the mode for each line of VRAM, sampled at horizontal middle of 800x600 screen, and used at begin of each lineTests done here : ppi/psg/cpctest.
=== Sniffing of a real Amstrad ===[[File: cpc_plus_m1arnoldemu_testbench_CPCTEST-r005-6.jpgpng]]Code name: Raptor
In r005.6, I listen reach successfully some arnoldemu tests to some wires of my Amstrad CPC 6128 plus, but I can't access VSYNC/calibrate more efficiently HSYNC output of CRTCinterrupt : ppi.bin, so I have to buy another model in order to do this testpsg. In fact you can listen at clock of Amstrad and transmit it to FPGA DCM componentbin, resulting a accelerated clock sequence, that's it, with FPGA DCM you can overclock output Amstrad clock signal in order to insert more operations, I use this tip for listening signals and save them inside starter kit asynchronous RAM (write, stop write, write, stop write... I’m a perfectionist paranoid.cpctest.bin.)
You can power Amstrad CPC using extension port, applying 5vGames unlocked by r005. By doing it6 : Sigma7, power down button of Amstrad doesn’t run. Using this way you reach a common 5v power between starterPac-kit and Amstrad. I connected wires from extension port directly to FPGAland, as they are used just for listeningGolden Tail.
=== ROM and RAM extension ===In r005.8, Prehistorik is running fine.
In r004, you have more RAM +512KB, and you can add ROMsr005.* LowerROM has 8.eZZ file extension* UpperROM has .e00 ot eFF file extension (hexa)4, arnoldemu testbench "cpctest" does fail :/
In r005.48.7, I add another UpperROM set : .f00 to .fFF file extension (hexa). If you press arnoldemu testbench "spacecpctest" during a reset_key ("page up" key), upperROM files used range from .f00 to .fFF instead of ranging from .e00 to .eFF. LowerROM .eZZ file extension is still used in both case.OK
==== TODO In r005.8.14 version, using default mode "MEM_wr: RAM 4MB extension ====quick", is OK. And Prehistorik II is running fine.
Why not ?In r005.8.16c29, arnoldemu testbench "cpctest" is OK (but it is a wip version :p)
=== Sound output =GA: TODO : MODE row buffer ====MODE does change at each begin of lines, not at begin of pixel drawn. Il ne faudrait pas penser que l'on puisse changer de mode plusieurs fois par ligne. En effet. c'est "impossible"! (jusqu'à preuve du contraire, le mode s'enclenche à chaque synchro horizontale (HBL).https://cpcrulez.fr/coding_logon35-le_gate_array.htm
==== PWM GA: Moustache testbench ====A homemade Testbench done firstly for helping Sorgelig to calibrate it's port of FPGAmstrad into MiSTer. But as Sorgelig core does run finer than mine (Pinball Dreams did pass ! WAIT_n:slow, CRTC 1, Brand name: Amstrad), I do then take back the good behavior using this testbench, resulting r005.8.16.1
Using It's a simple [[PWM]], data is entered at a certain speed, the [[PWM]] clock speedstress testbench around VSYNC/HSYNC/interrupt.
If you simulate the cat doesn't catch the line, this testbench does fail (that's a constant [[PWM]] output signal at middle range of voltage (state just small palette testbench). First array is about VSYNC length comparable between 0V a real CPC and 5V : 2an emulator.5V)Second array is about interrupt length. Stress is done by inserting NOP, it results an alternance of 0V and 5VNOPNOP, that result in a noise sound. In Arkanoid, this defect make some continues sounds instead of silents..NOPNOPNOP or else NOPNOPNOPNOP instruction before each measure.
My idea is generating a sound having a frequency upper than dog ultra sound, while I want to simulate a constant 2[https://github.5Vcom/renaudhelias/RubikCubePaletteCPC/blob/master/JDVPA%236_test/jdvpa6_moustache.dsk jdvpa6_moustache.dsk]
For this I do use two clocks entries in my [[PWM]] File: one about data entry, and another about algorithm executionJdvpa6 moustache-FPGAmstrad testbench.png|thumbnail|jdvpa6_moustache.dsk testbench]]
This result a high quality sound output ==== GA: Sorgelig formula ====GA instruction-timing formula (in addition to this nice [httpcompteur1MHz is 4MHz mod 4): --Sorgelig formula ://www.fpgaarcadewait_n((phase == 0) | (IORQ_n & MREQ_n) | no_wait) if compteur1MHz > 0 and (IO_REQ_R='1' or IO_REQ_W='1' or MEM_RD='1' or MEM_WR='1') then WAIT_n<='0'I put it inside OSD menu WAIT_n:quick in r005.com/library8.16.8.5c1Does pass easily plustest.dsk test 5, but not 9. Mister Amstrad does pass test 9, I misunderstood how its Z80 is hacked.htm Yamaha sound chip from fpgaarcade])
==== Stereo sound output ====Another great Sorgelig formula btw :[[File -- Sorgelig formula :STarKos1 21 FPGAmstrad_800x600.pngwire acc = (MREQ_n |none|STarKos 1.21 running on FPGAmstrad]]~RFSH_n) & IORQ_n; MREQ<=not(MREQ_n or not(RFSH_n));
Sound chip was modified in order to get channel A+B at left, and channel B+C at right.=== Z80 ===It was tested OK using [http://www.grimware.org/doku.php/documentations/software/starkos/start STarKos 1Architecture of Z80.21] sound tracker (track "Carpet")
In r005.8.14.1 STarKos does feel better using parameter "MEM_wr:slow" in OSD menu.
run"stk / esc / enter / enter / => / enter / space (wait) / esc / ctrl+F2 / \/ (bottom arrow) / space=== Z80: test of a real Zilog 80 ====[[File:Z80fx2bb.jpg]]Code name : Z80fx2bb, real Z80@2MHz (ctrl+F1 to go back into the disk menuinstead of 4MHz)on fx2bb extension card.
STarKos seems running PERFECTLY using A-Z80 instead of T80, please do contact me if you want a personalized fork version of CoreAmstrad using A-Z80 (I have just to switch a parameter : USE_AZ80:boolean[[http://www.youtube.com/watch?v=false; in FPGAmstrad_amstrad_motherboardYYnvkR5v3D0 http://www.vhd)youtube.com/watch?v=YYnvkR5v3D0]]
=== DONE: Another disk selector ===For it I plug all wires simply from 1 to 40. Some wires are cut, some are Vcc, others GND. Z80 output are directly connected, Z80 input are pull-up with red-red-red resistors (I like red), Z80 is powered 5v (pmod can give 5v using jumper). In fact z80 is so old component that powering it 5v does output 3.3v.
In first version fact the only difference between [[T80]] of FPGAmstrad (NEXYS2) I used switches for disk selection. As final FPGA platform doesn't have any switches setopencore and real Z80 is that [[T80]] runs on rising_edge, I have to add an BASIC instruction for and Z80 runs during low state. Test past with little modification of sequencer forcing itto do nothing during low state of z80, something like "OUT &CAFEresulting a downclock (memory is too overclocked with this sequencer modification),disk_number" perhaps using buffer on address bus and data bus could be finesolve this detail... but as it runs for me it is not a problem.
Since FPGAmstrad in NEXYS4, disk selection is done from keyboard, using "OUT &CAFE,disk_number" instruction.==== Z80: architecture ====A reset key was added also===== a) T80.vhdl ====="PRINT INP(&CAFE)" does print current disk selected number17 pages of source codes to read.
==== DONE : A advanced dsk drive ====Not analyzed yet completly.
Done on r004, I added also a second Drive in order to copy easily files from one disk to anotherContains the main workflow of Z80: current MCycle and its current TState.
Irregular sector size okContains T80_ALU.vhdl and T80_MCode.vhdl components.
You just have ===== b) T80_ALU.vhdl =====6 pages of source codes to select Drive A or B from OSD before selecting another dsk fileread.
Write is done directly on sdcard dsk file, so you Not analyzed yet completly. This analyse can save games, and write texts..certainly be wrong : wip.
You can now change disk without reset. And then play games using several disks.Contains flags : C N P X H Y Z S C : carry - set if result did not fit in the register N : negative? - last instruction was substract P : parity or overflow - overflow example : signed, 7F+7F=FE with overflow setted X : undocumented H : half carry - set if 4bit first bits of result did not fit in the register Y : undocumented Z : zero - set if result is zero S : sign - it is an input ?Contains ALU_Op : [ADD ADC SUB SBC AND XOR OR CP] ROT BIT [SET RES] DAA
[http://wwwALU_Op is the basic instructions of Z80 coded here.cpcwikiT80_ALU.eu/forum/amstrad-cpc-hardware/fdc-floppy-t80ds-detection/ CPCWiki forum - Amstrad CPC hardware - FDC floppy t80ds detection] : talk about FDC in MiST-board CoreAmstradvhdl is a slave, a service exposed to T80_MCode.vhdl throw T80.vhdl
==== DONE [[http: A advanced FDC (with write access and more) ====Since r004 "mecashark"//www.z80.info/decoding.htm § Disassembly tables]] shall make a cool ALU_Op quick reference card, the FDC implementation has write access !doesn't it ?
==== UNDONE : FAT32 fragmented files support = c) T80_MCode.vhdl =====Since advanced FDCFirst 5 pages, dsk files have and last 2 pages of source codes to be defragmentedread. Only ROMs Others pages are safe with a not defragemented sdcard.."always the same" architectually speaking.
==== TODO Not analyzed yet completly. This analyse can certainly be wrong : SNAP DSK ====Add an option in OSD MENU : "SNAP DSK"wip. Does create a copy of current disk in current drive into "SNAP[number].DSK". Heuristic for number : file count (at boot, incremented at each snap dsk done)
==== TODO Gives instructions lengh : fix message "This program will not run in this environment. Press any key" ====HartOz The core does not support the bundled CP/M+ software. With a valid working CP/M+ Disc1 image mountedMCycles, TStates (please remark the systems returns with the following message after issuing the |cpm command's' at end of theses words. "This program will not run in this environment. Press any key"Due to using wrong language version of CP/M+ disc (cpmpluf1.dsk is french version of CP/M+), in [[Filehttp:Cpmpluf1//www.dskzilog.png|thumbnail|CPcom/M+ fr disk inserted (cpmpluf1docs/z80/um0080.dsk)pdf Z80 doc]]each instruction is timing described using "M Cycles" and "T States" vocabulary.
It's a "Wrong disk for your configurationcontroler" message seen in one-disk version of "Batman Forever" demo (two separate disk version runs fineproof : you have some Set_*_To outputs), in forum they say that dsk image is using "bad track numbers", in fact when looking at a Track-Info with side 1 (instead of 0), track and side are correct in Track-Info but side is not ok in Sector-Info, normaly track/side are ignored in Sector-Info (Track-Info is used for that)does gives orders to T80_ALU.vhdl throw T80.. but still having the message, something else seems also wrong.vhdl
Do fix also message Actions of this controler are :* ALU_Op : the action !* I_DJNZ I_CPL I_CCF I_SCF I_RETN I_BT I_BC I_BTR I_RLD I_RRD I_INRC : actions not for ALU (wiring input/ouput, changing flags...)* Save_ALU/PreserveC : an option about register "Bad Commanderased or not" while running a at next instructionInstructions not existing file on diskcoded in T80_MCode.vhdl but in T80.vhdl (strange, barbarian part of code ?) :* Jump/E/XY Call RstP LDZ LDW LDSPHL Special_LD ExchangeDH/Dp/AF/RS
Certainly linked to ''Orion PrimesInc_WZ register : take a look at [[http://www.dsk'righto.com/2014/10/how-z80s-registers-are-implemented-down.html § The WZ temporary registers]. It' loading problems a tmp internal register in fact.
=== TODO = Z80: A X/Y input Some bad instruction timing analysis ====Based on [[http://www.winape.net/ WinAPE>download>Plus test>plustest.dsk]] testbench, mapped using [[http://clrhome.org/table/ Z80 instruction set - ClrHome]], instruction described then in [[http://www.zilog.com/docs/z80/um0080.pdf Z80 doc]], against [[http://www.winape.net/ WinAPE]] passing testbench timing.
I want to work also on screen-pen entry, is there a manner to detect an analog X/Y as pen or gun ? YES : [http://javaSolved in r005.cpc-live8.com/gx400016.php Markus Hohmann] does it, he implements the lightgun on JavaCPC-GX4000 using mouse :3 (WAIT_n generator)
http==== Z80: Some bad instruction analysis ====Based on [[https://cpcrulez.fr/hardwareapplications_CPM-pistoletutil-magnum_light_phaser_ACPCzexall.htmZexall: Z80 instruction set exerciser]], running fine in JavaCPC.
register 11,12 and 13 ?Solved in r005.8.16.3 by Sorgelig (T80 fixes) - valided
=== DONE= Z80: A SCART output ED B9 cpd(r) / ED B1 cpi(r) ====<s>Problem here : CPDR and CPIR has same implementation than ED A9 CPD and ED A1 CPI.</s>
In order to plug FPGAmstrad on TV, and help debuggingSolved by Sorgelig (does not pass plustest. And also to test a simple scan-doublerdsk testbench 5 in r005.8.16.2 but does pass it on Sorgelig MiSTer fork version)
r005c17 : experimental version, original signal TV output In fact it is running fine, with OSD menu. Have to add a flag more difficult instruction that I was thinking, if you watch at it, it shall take only 4 NOPs maximum but in mistplustest.ini instead of using OSD menudsk it does take 6/4 NOPs.scan-doubler doesn't run ok in mode 2In fact C9 RET seem also used here, as sub instruction. I remark that CPD and CPI does take 4 NOPs, so here CPDR/CPIR does not has strange offset with Arkanoid same implementation than CPD/CPI (vertical display games), so it unvalidated I was wrong : only original TV output will be added to r004 CPIR/CPIR is implemented in r005.T80)
Done in r005 .8.16.4 : VGA 60H/TV 50Hzjust added a TState (TStates <= "110";) on case 3, that way plustest.dsk tb 5 does succeed.
==== Z80: TODO : an OSD option to enable scancpc-doubler power testbench ====
scan[http://www.cpc-doubler (simple TV to VGA converter) doesn't run ok in mode 2, but there is some many recent demo effect that doesn't pass using current VGA 72Hz implementationpower. Have to try to insert both VGA implementationscom/index.php?page=detail&num=12883 CPC-Power Z80 FULL TEST (UK) (2012) - UTILITAIRE]
core_r005c18 seems having a scan-doubler output, have to merge itSome errors detected in r005.8.4 (test done by Philippe D.)
==== DONE : A SCART output with border ====Some errors detected in r005.8.16.3
Original output signal has no border, I have to implement the original border 2 errors left only in TV moder005.8.16.6 (thanks to Sorgelig hard work in T80)
Priority==== Z80: HIGH! winape testbench ====[http://www.winape.net/download/plustest.zip WinAPE plustest.zip (asked by Markus Hohmannincluding Instruction and Interrupt timing tests)]
Done in r005=== DSK ===It's data, insertion of disk.8.14.2
==== DONE DSK: move SCART parameter into mist.ini Another disk selector ====Doing like in other cores : do use the global "scandoubler" option in mist.ini to switch between VGA and TV mode.
==== DONE : mix SCART H and V sync into HV sync In first version of FPGAmstrad (sort of C syncNEXYS2) ====[http://github.com/mist-devel/mist-binaries/issues/35 Amstrad CPC core · Issue #35 · mist-devel-mist-binaries · GitHub] : SCART TVs expect a composite sync. The VGAs vsync is connected the SCART pin I used to detect a RGB signal and is constantly driven highswitches for disk selection. A TV will not cope with a video signal with separate H and V sync. Bu titAs final FPGA platform doesn's usually sufficient t have any switches set, I have to xor hsync and vsync to get a csync acceptable add an BASIC instruction for many TVs.So it, something like this Vsync=1; Hsync=old_Vsync xor old_Hsync;Done in r005.8.14"OUT &CAFE,disk_number" could be fine.1
==== DONE : refactor of Parrot PAL signal ====I found a running 15kHz TVSince FPGAmstrad in NEXYS4, with [http://github.com/mist-devel/mist-board/blob/master/tutorials/soc/lesson11/lesson11.png mist-board tutorial lesson11 Parrot PAL] running finedisk selection is done from keyboard, but not with CoreAmstrad r005using "OUT &CAFE,disk_number" instruction.8A reset key was added also.14.1. It's the same TV I used some years ago at festival with original CPC. I have to refactor Parrot tutorial and adapt it on CoreAmstrad in order to generate a better TV signal quality"PRINT INP(&CAFE)" does print current disk selected number.
Done in r005.8.14.2
In theory, simple_GateArrayInterrupt.vhd shall have : vsync_azrael<=etat_monitor_vhsync(2); hsync_azrael<=etat_monitor_hsync(2); if hSyncCount=2+4 thenIn practice - in r005.8.14.2 - here we have = DSK: vsync_azrael<FAT32 fragmented files support ==etat_monitor_vhsync(1); hsync_azrael<=etat_monitor_hsync(1); if hSyncCount=1+4 thenThis way screen is nicely centered but CPCWiki rule "The HSYNC is modified before being sent Since advanced FDC, dsk files have to the monitorbe defragmented. It happens 2us after the HSYNC from the CRTC and lasts 4us when HSYNC length is greater or equal to 6Only ROMs are safe with a not defragemented sdcard. If R2=46, and HSYNC width is 14 then monitor hsync starts at 48 and lasts until 51." is not respected.
Test about centering screen are done ZX-Uno is using "BORDER 0"simple FDC, this way border is ignored and does interact with HSYNC/VSYNC screen synchronisationnot impacted here.
=== DONE = DSK: CRTC1 TODO : arnoldemu testbench ====r004.8 '''arnoldemu testbench: a better CRTC/Gateway implementation, following better JEmu (JavaCPC) one... but it is a CRTC1 (but a better ONE)Some bugs came from PPI also (keyboard bugs in particular), solved in r004.8fdctest'''
==== DONE : CRTC0 ====
CRTC0 seems the best one, some demo does cry when detecting a poor CRTC1 (CRTC1 seem a low cost version of CRTC0). I have to implement a CRTC0 instead of my current CRTC1...
In fact CRTC1 is the best one. CRTC2 is the low cost version. CRTC0 did appears before CRTC1.
Done in r005.8.14. Detected as CRTC0 by WakeUp! - "Enjoy the show" message displayed.
In r005.8.15. WakeUp! (CRTC0/MEM_wr quick) detected as Emu first time, and after a quick reset, does say detected as CRTC0.
==== DONE : CRTC1 detection ====
I don't remember exactly, but in r005.8.4, one of "Midline Process"/"From Scratch"/"Pheelone" demo does crash due to a "CRTC1 needed" message : my CRTC1 seems not detected as a true CRTC1... If's "From Scratch" that does display this message in fact.
Done in r005.8.14 : Still Rising (Vanity) demo can be launched, better using "MEM_WR:slow" mode.
[http://quasar.cpcscene.net/doku.php?id=coding:test_crtc Test CRTC - Quasar Net]
=== TODO : Interlaced scanlines ===
Interlaced scanline is an effect existing in CRTC (register R8) used by Wolfenstrad demo
Seen also at begin of '''R-Typeee.dsk''' ("stereo soundtrack" message's picture), and seem also used in a lot of recent demos as "flipping lace" effect.
Scanline is also used just at begin of '''Pinball_Dreams__PREVIEW.DSK''' (eagle draw) - in fact I've got a doubt here, it seems more about a problem of HSYNC edge choice of alignement here.
[http://cpc.sylvestre.org/technique/technique_identifier_crtc.html Les Sucres en Morceaux - Amstrad CPC - Identifier les CRTC]
OUT &BC00,8
OUT &BD00,3
[http://quasar.cpcscene.net/doku.php?id=coding:test_crtc Test CRTC - Quasar Net]
L'écran passe en 100Hz, les registres 4 et 7 doivent être doublés pour retomber sur 50Hz
=== DONE : Scanlines ===
Here effect is about simulating CRT (not CRTC.R8) original screen. There is several way to implement it.
Here, truly one line out of two is 1/2 darker. By visual effect this result in "a thin full black horizontal line".
[[File:FGPAmstrad cc withoutScanlines.png|thumbnail]]
[[File:FGPAmstrad cc withScanlines.png|thumbnail]]
=== DONE : Monochrome option ===
Add an option to turn screen into green monochrome mode (in mode TV and in mode VGA)
done in r005.8.9.2 (Soleil Vert demo)
[[File:Soleil vert CoreAmstrad.png|thumbnail]]
[http://cpc.sylvestre.org/technique/technique_coul1.html Les Sucres en Morceaux - Couleurs - 1 - Les couleurs du CPC]
==== DONE : Monochrome OSD ====
Could be great having the OSD in monochrome when monochrome is selected and scanlined when scanline is selected
Done in r005.8.14.4
=== TODO : Ethernet ===
Integration of "ethernec.v".
=== DONE : arnoldemu's testbench fdctest ===
arnoldemu's testbench to pass : test/fdctest/fdctest/fdctest.dsk
Have also to fix theses "Bad Command" responses from fdc (it seems that when you don't reach a track, you have to send back the current track instead of this "Bad Command" signal). Test : 30YMD demo, "disk change" message not running correctly, "another disk inserted" is not detected in this demo.
==== arnoldemu's testbench results ====:
CoreAmstrad r005.8.15
* 27FAIL01/29FAIL01 : read_track6/read_track10 - very big sector size counter not implemented (more than 512B)
* 60FAIL01 : format2 - format command not implemented (this test is slow)
==== TODO Perhaps dsk does go into sleep after a certain time of no use, and then takes a certain time to wake up when reused : arnoldemu's second testbench ====a timeout for turning the motor off. Perhaps overrun of FDC does turn the motor off.
[http://www.cpctech.orgcpc-live.ukcom/test.zip http:docs/upd765a/wwwnecfdc.cpctech.org.uk/test.zip] arnold test last update. Folder disc/htm During disk data transfers between the FDC and the processor, tests : "seekvia the data bus, recalibratethe FDC must be serviced by the processor every 27µs in the FM mode, sense interrupt statusand every 13µs in the MFM mode, sense drive statusor the FDC sets the OR (Over Run) flag in Status Register 1 to a 1 (high), write protect"and terminates the Read Data Command.
=== TODO : github migration ===arnoldemu's second testbenchHave to migrate source-code repository from renaudhelias github to mist-devel github[http://www. And also update each url in head of source-code filescpctech.org.uk/test.zip http://www.cpctech.org.uk/test.zip] arnold test last update. Folder disc/, tests : "seek, recalibrate, sense interrupt status, sense drive status, write protect"
=== PPI ===
Problematic here : Keyboard detection versus VSYNC signal versus interrupt cycle.
==== DONE PPI: A better PIO ====
I'm looking after a great implementation of PIO, in original schematic of Amstrad, keyboard (output, not input) is mapped behind Yahama chip behind PIO.
In original schematic, PIO is the only one component having a low state reset (0), I think that imply a 0 value as state init of internal components variable. Data bus of Z80 seems having a pull-up state (read 1 when nothing is plugged), for example a unplugged ROM does respond xFF in data-bus.
Update : arnoldemu's testbench PPI passed. ==== TODO PPI: Yamaha clock ====
In r005.5 I build the Yamaha clock from GA. Unlocking "Saboteur 2" game.
Yamaha clock (YM2149_linmix_AmstradStereo.vhd) is used only for "sound algorithm", not for setting/getting registers (registers are set using "BDIR BC2 BC1" wires), so I have to overclock the setting/getting register clock to simulate the original behaviour...
==== DONE PPI: PPI clock ====
PPI in original schematic does not have clock ! So I have to overclock this one to simulate the original behaviour...
Overclocked at 16MHz.
=== TODO = PPI: a better border heuristic arnoldemu testbench ====Using winape arnoldemu's testbench (plustest), test 2 does show somes problems while border does go out of screen, negative border does hide line itselfPPI passed.
=== TODO : AMX mouse support SOUND ===Asked by KLNHOMEALONEPWM.
=== UNDONE = SOUND: pause Z80 while OSD is displayed PWM ====Cause playing Double Dragon II without "pause", is quite difficult.
Or else using "Pause" key ?Using a simple [[PWM]], data is entered at a certain speed, the [[PWM]] clock speed.
Can have border effect in sound If you simulate a constant [[PWM]] output signal at middle range of voltage (perhaps sound can be "freeze" state just between 0V and then still up5V : 2.5V), it results an alternance of 0V and 5V, that result in a noise sound. In Arkanoid, this defect make some continues sounds instead of silents...)
=== TODO : tapes ===Do read My idea is generating a sound having a frequency upper than dog ultra sound, while I want to simulate a constant 2.CDT files also5V.
For this I think @ralferoo had already written FPGA code for tape reading for his FPGA CPC. Maybe you can borrow some code from him? Brycedo use two clocks entries in my [[PWM]] : one about data entry, and another about algorithm execution.
=== DONE BUT SEEMS USELESS This result a high quality sound output (in addition to this nice [http: welcome VGA signal ===//www.fpgaarcade.com/library.htm Yamaha sound chip from fpgaarcade])
While bootloader is not fully started, do display a lighter screen ==== SOUND: Stereo sound output (not darker pixels as original screen color CPC depth using more resistors), as it VGA should be nicely centered at each boot====[[File:STarKos1 21 FPGAmstrad_800x600. And then after come back to original CPC pixel depthpng|none|STarKos 1.21 running on FPGAmstrad]]
Some VGA does detect FPGAmstrad resolution just if pixels are ligtherSound chip was modified in order to get channel A+B at left, so I turn them lighter during and channel B+C at right.It was tested OK using [http://www.grimware.org/doku.php/documentations/software/starkos/start of engineSTarKos 1. Normaly a press into reset button (the one front the sdcard entry) does solve directly this problem 21] sound tracker (you can also turn on screen before MiST-board with this sort of screenstrack "Carpet")
I tryed also [http://githubIn r005.com/mist-devel/mist-binaries/tree/master/cores/menu menu core project] with my stupid screen, as it normally I can power on MiST-board before screen for FPGAmstrad (switching core 8.14.1 STarKos does the stuff here also)feel better using parameter "MEM_wr:slow" in OSD menu.
Tryed in r005.8.14.4 : lighter pixels during bootload. Also with a full white screen. run"stk / esc / enter / enter / => / enter / space (wait) / esc / ctrl+F2 / \/ (bottom arrow) / space(ctrl+F1 to go back into the disk menu)
This solution does not fix the problem STarKos seems running PERFECTLY using A-Z80 instead of "stupid screen"T80, but reveals something interesting about the defect (next chapter) ==== SAMSUNG 16/9 tests ====Using lighter pixels full white screen during bootload show please do contact me that screen doubts between two positions : a perfect centered 4/3 with 6.5 centimeters horizontal border each; and a starting 16/9 at left, crop at 6.5 centimeters left. Without lighter pixels full white screen, the crop of image does change, moving into first displayed characters : in fact in SAMSUNG menu, the position of screen is not 50 50, if you put 50 50 you come back to "lighter pixels full white screen" defect. So here screen begining at first char displayed on screen is want a second defect, but a small one, as you personalized fork version of CoreAmstrad using A-Z80 (I have just have to set 50 50 in SAMSUNG menu. So back to previous bug : screen doubt between two positions "switch a perfect centered 4/3 with 6.5 centimeters horizontal border each; and a starting 16/9 at left, crop at 6.5 centimeters left".When displaying a game, in fact, in found two different case in "perfect centered 4/3" case , this case is not so perfect, it does also doubts between two positions parameter : * one time screen does crop at 6.5 left and right, changing the screen vertical position using menu does translate the image cropping left and right at fix position USE_AZ80: 6.5 centimeters fix black border. About extra 1 centimeter pixels boolean: image =false; in middle of image does move, but not the borders at allFPGAmstrad_amstrad_motherboard.* a second time image does move perfectly (completely/totallyvhd) left and right without crop, and if centered has 6.5 black border left and right. This time image seems complete but crushed. === TODO = SOUND: snapshoot purpose Dual SID ====Like in emulators, do something to go back in time while running a game.Why not ?
----
In order to get a better external RAM performance, and getting more luck about porting my project into others FPGA platform, I do now use a "Mirror VRAM" : external is just used by Z80 read and write (no more clock sequence finally ^^'). And a write in video RAM zone (like "poke &C000,255") does just write also in another parallel RAM, a FPGA internal RAM, that I call VRAM, this VRAM can be written at a certain speed and read at another for VGA purpose (FPGA internal RAM can be used like that)
=== USB joystick Joystick ===
Before learning final platform and its embedded controlers (USB joystick with a controler, is just 7 wires : left right up down buttonX buttonY buttonZ), and after having destroyed 12 collector original joysticks during tests... I did some research about simply connecting a modern USB joystick into FPGA. It was a part of my Agile Method run, I worked about two months on it.
http://www.youtube.com/watch?v=fh4v4OXridc
USB is just a state machine (welcome how are you today, show me your state, show me your state, show me your state....), encoding (have to read USB manual), you can use some usb sniffer softwares software to decode them (wireshark unix version does it fine). Sniffer software does not show low level messages (ack ko ok) but does show the high level messages (ones that show that a button is pressed or not)
As it is just encoding, you can capture signals and show that they differ only when you do unpress or press a button.
http://www.ulule.com/usb-paf (unfunded) => but MiST-board final platform does offer USB pro competition Joystick compatibility <3 <3 <3
==== A fork of USB Joystick by The EMARD ====
A fork of this minimalistic USB Joystick controler by The EMARD, going further :
http://github.com/emard/fpga-usbhid-host
----
My own made program does it with poor serial port, so for dumping all RAM content it takes about 3 hours, and for dumping Amstrad RAM part it is about 15 minutes.
On [[http://www.digilentinc.com/Products/Detail.cfm?Prod=NEXYS2 Diligent NEXYS2 official page]], you can download a "Onboard Memory controller reference design" that contains explanation and VHDL source code about dumping on RAM/ROM of NEXYS2 directly from PC (usb port). I didn't tested this yet, but it is certainly a nicer approach :P
==== FPGA internal RAM size ====
==== Metal case ====
It's a true final platform.
=== Why ZX-Uno platform ===
==== Jepalza port ====
Jepalza has ported FPGAmstrad on it, A lot of thanks Jepalza !
==== Same FPGA as NEXYS2 500kgates starter kit ====
It's the opportunity to update the original simple prototype schematic.
==== low-cost FPGA ====
==== simple and over-documented ====
As the original, it is using simple components :
* simple VGA: it is using a 640x480 centered VGA display at 60Hz
* simple DSK: a dsk here is simply flatten into RAM parts
* simple bootloader: the bootloader is read-only, loading data using SPI protocol, and slave of a FAT32 state machine deploying this data into RAM just before turning on Z80.
* simple disk selection: the first disk is inserted at boot, and the "page-up" bottom does reset+insert the next disk.
* simple GateArray : CRTC0 only
and is over-documented... here !
==== Xilinx schematics ====
Schematics, as on original, are quite small, except the motherboard on that is comparable to original CPC motherboard schematic.
==== fork and merge ====
This version of FPGAmstrad is a 2011's fork of NEXYS2's FPGAmstrad, merged with '''last validated components''' of MiST-board version.
This way no useless options are added, and the source code stay clear !
----
A schematic developed in order to be comparable to original documentation schematic is nice. FPGAmstrad is composed of 3 schematics :
* amstrad_motherboard : comparable to original Amstrad schematic.
* amstrad_video : does manage a true VGA output, using a an internal VRAM.
* bootloader_sd : sdcard bootloader, in order to load ROM and dsk at boot, from sdcard.
Now I can use my 16KB free RAM in VRAM double buffer. Reaching a full FGPAmstrad project deploy on MiST-board, unlocking others games : it is what is done in realise 002 of Amstrad core. I tested ChaseHQ does now run fine.
== ZX-Uno - Core Developer's Notes ==
=== Why I destroyed the PPL ===
NEXYS2's FPGAmstrad version is using a PPL (a DCM : Digital Clock Manager), just for half part of clocks generation.
Then comes the sequencer (the counter used to divise time) that does not respect "Timing Contraints good practice", forcing then adding a "I dislike good pratice" sentence on .ucf file like that :
IN "XLXI_512/XLXI_579/COUNT_1_BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
Having half of clocks generated by a PPL results on a project running fine one time on both compilation : you add some normal lines of code, and then you toss a coin.
Then I tryed, as on MiST-board version to manage all clocks from an unique PPL (good practice !), centering all clocks on one component, removing counter and also all logical "NOT" on clocks wires (good practice !), resulting then... in a electronic circuit that does not enter inside my FPGA chip. Damn.
So I go back to dark side, removing PPL. Recalibrating all clocks (this time "rising_edge against falling_edge" instead of "same edges" per component's process), and thinking "no more Time Constraints, no more problems around". And you know what ? I got that :
WARNING:Route:464 - The router has detected a very dense, congested design. It is extremely unlikely the router will be able to finish the
design and meet your timing requirements. To prevent excessive run time the router will change strategy. The router will now work to
completely route this design but not to improve timing. This behavior will allow you to use the Static Timing Report and FPGA Editor to
isolate the paths with timing problems. The cause of this behavior is either overly difficult constraints, or issues with the
implementation or synthesis of logic in the critical timing path. If you are willing to accept a long run time, set the option "-xe c" to
override the present behavior.
Intermediate status: 929 unrouted; REAL time: 3 hrs 35 secs
Damn, 3 hrs 35 secs of compiling... Then I used my brain and think that it is trying to stupidly clocking my "reset_key" wired between my keyboard clock and my bootloader clock... so I had this set of instructions inside SDRAM_FAT32_LOADER.vhd :
attribute keep : string;
attribute keep of key_reset : signal is "TRUE";
attribute clock_signal : string;
attribute clock_signal of key_reset : signal is "NO";
And tadam, less than half of hour to compile now ! and on a determinist way.
This formula does run also on bus (dsk_info bus wire coming from SDRAM_FAT32_LOADER to simple_DSK)
=== Internal FPGA RAM (VRAM) config ===
The internal dual RAM (written at 4MHz by Z80 and readden at 25MHz by VGA) are configured as "WRITE FIRST", "READ DOESN'T CARE".
aZRaEL_vram2vgaAmstradMiaow.vhd (the VRAM to VGA output part) has several manual counter offset calibrations, called "bug_*", it seems this component does not know counting right when reaching 25MHz (in fact it is, "mod" instruction does suffer a lot by here)
=== palette_D and aZRaEL's counters derailment ===
Compiler does detect when somes wires of a bus are not used, and when this bus is scanned by several counter derailing it results some data missing (this pixels normaly come from this offset, but is finaly calibred at this offset, so I plug it here and compiler does not thrust me, saying it's plug to an unused wire so does compile all that to GND... black screen)
Solution : using all wires of palette_D, taking care the compiler does not remove an "useless" wire from bus, and do calibrate manualy the derailing counters (all that "bug_*" constants inside aZRaEL_vram2vgaAmstradMiaow.vhd)
== Source code ==
=== FPGAmstrad source code (Xilinx)===
The project binary downloadable on [[#How_to_assemble_it]] section contains in fact source code and the binary file (.bit)
Compiling OK in Quartus II 13.0 (Altera IDE), and a few in ISE Design Suite 14.7 (Xilinx IDE) - I have to report back some modifications from my deploy platform(Altera MiST-board) to my dev platform (Xilinx NEXYS4 from Digilent Inc.)
=== ZX-Uno FPGAmstrad source code (Xilinx) ===
[http://github.com/renaudhelias/FPGAmstrad ZX-Uno FPGAmstrad source code]
----
* [http://www.cpcmania.com CPCMANIA] ''plug Amstrad on TV''
* [http://bellaminettes.com Bellaminettes] fr ''Artist drawer -nice girls- from ACBM magazine - Les puces informatiques - Sasfepu''
== Appendix ==
=== MiST-board special features ===
Bulk of effort done/TODO-list, especially for the MiST-board's CoreAmstrad implementation.
==== ROM/RAM ====
==== ROM/RAM : extension ====
In r004, you have more RAM +512KB, and you can add ROMs.
* LowerROM has .eZZ file extension
* UpperROM has .e00 ot eFF file extension (hexa)
In r005.4, I add another UpperROM set : .f00 to .fFF file extension (hexa). If you press "space" during a reset_key ("page up" key), upperROM files used range from .f00 to .fFF instead of ranging from .e00 to .eFF. LowerROM .eZZ file extension is still used in both case.
==== ROM/RAM: TODO : RAM 4MB extension ====
Why not ?
==== VIDEO ====
===== VIDEO: A SCART output =====
In order to plug FPGAmstrad on TV, and help debugging. And also to test a simple scan-doubler.
r005c17 : experimental version, original signal TV output is running fine, with OSD menu. Have to add a flag in mist.ini instead of using OSD menu.
scan-doubler doesn't run ok in mode 2, and has strange offset with Arkanoid (vertical display games), so it unvalidated : only original TV output will be added to r004 in r005.
r005 : VGA 60H/TV 50Hz.
===== VIDEO: An OSD option to enable scan-doubler =====
scan-doubler (simple TV to VGA converter) doesn't run ok in mode 2, but there is some many recent demo effect that doesn't pass using current VGA 72Hz implementation. Have to try to insert both VGA implementations (=> done in r005.8.15.2)
On Sorgelig fork, the scandoubler does run ok in mode 2 (but still not centered correctly on VGA 16/9)
===== VIDEO: A SCART output with border =====
Original output signal has no border, I have to implement the original border in TV mode.
Priority: HIGH! (asked by Markus Hohmann)
Done in r005.8.14.2
===== VIDEO: move SCART parameter into mist.ini =====
Doing like in other cores : do use the global "scandoubler" option in mist.ini to switch between VGA and TV mode.
===== VIDEO: mix SCART H and V sync into HV sync (sort of C sync) =====
[http://github.com/mist-devel/mist-binaries/issues/35 Amstrad CPC core · Issue #35 · mist-devel-mist-binaries · GitHub] :
SCART TVs expect a composite sync. The VGAs vsync is connected the SCART pin used to detect a RGB signal and is constantly driven high. A TV will not cope with a video signal with separate H and V sync.
Bu tit's usually sufficient to xor hsync and vsync to get a csync acceptable for many TVs.
So something like this
Vsync=1;
Hsync=old_Vsync xor old_Hsync;
Done in r005.8.14.1
===== VIDEO: refactor of Parrot PAL signal =====
I found a running 15kHz TV, with [http://github.com/mist-devel/mist-board/blob/master/tutorials/soc/lesson11/lesson11.png mist-board tutorial lesson11 Parrot PAL] running fine, but not with CoreAmstrad r005.8.14.1. It's the same TV I used some years ago at festival with original CPC. I have to refactor Parrot tutorial and adapt it on CoreAmstrad in order to generate a better TV signal quality.
Done in r005.8.14.2
In theory, simple_GateArrayInterrupt.vhd shall have :
vsync_azrael<=etat_monitor_vhsync(2);
hsync_azrael<=etat_monitor_hsync(2);
if hSyncCount=2+4 then
In practice - in r005.8.14.2 - here we have :
vsync_azrael<=etat_monitor_vhsync(1);
hsync_azrael<=etat_monitor_hsync(1);
if hSyncCount=1+4 then
This way screen is nicely centered but CPCWiki rule "The HSYNC is modified before being sent to the monitor. It happens 2us after the HSYNC from the CRTC and lasts 4us when HSYNC length is greater or equal to 6. If R2=46, and HSYNC width is 14 then monitor hsync starts at 48 and lasts until 51." is not respected.
Test about centering screen are done using "BORDER 0", this way border is ignored and does interact with HSYNC/VSYNC screen synchronisation.
===== VIDEO: CRTC1 =====
r004.8 : a better CRTC/Gateway implementation, following better JEmu (JavaCPC) one... but it is a CRTC1 (but a better ONE)
Some bugs came from PPI also (keyboard bugs in particular), solved in r004.8
===== VIDEO: CRTC1 detection =====
I don't remember exactly, but in r005.8.4, one of "Midline Process"/"From Scratch"/"Pheelone" demo does crash due to a "CRTC1 needed" message : my CRTC1 seems not detected as a true CRTC1... If's "From Scratch" that does display this message in fact.
Done in r005.8.14 : Still Rising (Vanity) demo can be launched, better using "MEM_WR:slow" mode.
[http://quasar.cpcscene.net/doku.php?id=coding:test_crtc Test CRTC - Quasar Net]
===== VIDEO: TODO : Interlaced scanlines =====
Interlaced scanline is an effect existing in CRTC (register R8) used by Wolfenstrad demo
Seen also at begin of '''R-Typeee.dsk''' ("stereo soundtrack" message's picture), and seem also used in a lot of recent demos as "flipping lace" effect.
Scanline is also used just at begin of '''Pinball_Dreams__PREVIEW.DSK''' (eagle draw) - in fact I've got a doubt here, it seems more about a problem of HSYNC edge choice of alignement here.
[http://cpc.sylvestre.org/technique/technique_identifier_crtc.html Les Sucres en Morceaux - Amstrad CPC - Identifier les CRTC]
OUT &BC00,8
OUT &BD00,3
[http://quasar.cpcscene.net/doku.php?id=coding:test_crtc Test CRTC - Quasar Net]
L'écran passe en 100Hz, les registres 4 et 7 doivent être doublés pour retomber sur 50Hz
===== VIDEO: Scanlines =====
Here effect is about simulating CRT (not CRTC.R8) original screen. There is several way to implement it.
Here, truly one line out of two is 1/2 darker. By visual effect this result in "a thin full black horizontal line".
[[File:FGPAmstrad cc withoutScanlines.png|thumbnail]]
[[File:FGPAmstrad cc withScanlines.png|thumbnail]]
===== VIDEO: Monochrome option =====
Add an option to turn screen into green monochrome mode (in mode TV and in mode VGA)
done in r005.8.9.2 (Soleil Vert demo)
[[File:Soleil vert CoreAmstrad.png|thumbnail]]
[[File:Soleil vert CoreAmstrad scandb50Hz.png|thumbnail]]
[http://cpc.sylvestre.org/technique/technique_coul1.html Les Sucres en Morceaux - Couleurs - 1 - Les couleurs du CPC]
TODO : alternative color, but cool ones : yellow (green) blue orange pink.
===== VIDEO: Monochrome OSD =====
Could be great having the OSD in monochrome when monochrome is selected and scanlined when scanline is selected
Done in r005.8.14.4
===== VIDEO: TODO : Scanline during monochrome + scandb50Hz modes =====
soleil vert demo display result is best using scandb50Hz mode (r005.8.16c29) because it does alternate two pictures at 25Hz, seeming then like a fixed image for humans.
But my scandb50Hz option does not enable yet the scanline effect that could improve her agains this demo. To do.
===== VIDEO: USELESS : welcome VGA signal =====
While bootloader is not fully started, do display a lighter screen output (not darker pixels as original screen color CPC depth using more resistors), as it VGA should be nicely centered at each boot. And then after come back to original CPC pixel depth.
Some VGA does detect FPGAmstrad resolution just if pixels are ligther, so I turn them lighter during start of engine. Normaly a press into reset button (the one front the sdcard entry) does solve directly this problem (you can also turn on screen before MiST-board with this sort of screens)
I tryed also [http://github.com/mist-devel/mist-binaries/tree/master/cores/menu menu core project] with my stupid screen, as it normally I can power on MiST-board before screen for FPGAmstrad (switching core does the stuff here also)
Tryed in r005.8.14.4 : lighter pixels during bootload. Also with a full white screen.
This solution does not fix the problem of "stupid screen", but reveals something interesting about the defect (next chapter)
===== VIDEO: TODO : SAMSUNG 16/9 tests =====
Using lighter pixels full white screen during bootload show me that screen doubts between two positions : a perfect centered 4/3 with 6.5 centimeters horizontal border each; and a starting 16/9 at left, crop at 6.5 centimeters left.
Without lighter pixels full white screen, the crop of image does change, moving into first displayed characters : in fact in SAMSUNG menu, the position of screen is not 50 50, if you put 50 50 you come back to "lighter pixels full white screen" defect. So here screen begining at first char displayed on screen is a second defect, but a small one, as you just have to set 50 50 in SAMSUNG menu.
So back to previous bug : screen doubt between two positions "a perfect centered 4/3 with 6.5 centimeters horizontal border each; and a starting 16/9 at left, crop at 6.5 centimeters left".
When displaying a game, in fact, in found two different case in "perfect centered 4/3" case , this case is not so perfect, it does also doubts between two positions :
* one time screen does crop at 6.5 left and right, changing the screen vertical position using menu does translate the image cropping left and right at fix position : 6.5 centimeters fix black border. About extra 1 centimeter pixels : image in middle of image does move, but not the borders at all.
* a second time image does move perfectly (completely/totally) left and right without crop, and if centered has 6.5 black border left and right. This time image seems complete but crushed.
During ZX-Uno merged, I found two bug on VGA implementations (true ones ?), first being horizontal and vertical counter not reaching VTot/HTot (one clock tic missing), and second the horizontal counter limited to 1024 not reaching HTot that seems more than 1024. Perhaps, if this bugs are valided as it, do go back on original 800x600@72Hz modeline formula.
==== DSK ====
===== DSK: A advanced dsk drive =====
Done on r004, I added also a second Drive in order to copy easily files from one disk to another.
Irregular sector size ok.
You just have to select Drive A or B from OSD before selecting another dsk file.
Write is done directly on sdcard dsk file, so you can save games, and write texts...
You can now change disk without reset. And then play games using several disks.
[http://www.cpcwiki.eu/forum/amstrad-cpc-hardware/fdc-floppy-t80ds-detection/ CPCWiki forum - Amstrad CPC hardware - FDC floppy t80ds detection] : talk about FDC in MiST-board CoreAmstrad.
Since r004 "mecashark", the FDC implementation has write access !
===== DSK: TODO : SNAP DSK =====
Add an option in OSD MENU : "SNAP DSK". Does create a copy of current disk in current drive into "SNAP[number].DSK". Heuristic for number : file count (at boot, incremented at each snap dsk done)
===== DSK: HOWTO: fix message "This program will not run in this environment. Press any key" =====
HartOz
The core does not support the bundled CP/M+ software.
With a valid working CP/M+ Disc1 image mounted, the systems returns with the following message after issuing the |cpm command.
"This program will not run in this environment. Press any key"
Due to using wrong language version of CP/M+ disc (cpmpluf1.dsk is french version of CP/M+)
[[File:Cpmpluf1.dsk.png|thumbnail|CP/M+ fr disk inserted (cpmpluf1.dsk)]]
"Wrong disk for your configuration" message seen in one-disk version of "Batman Forever" demo (two separate disk version runs fine), in forum they say that dsk image is using "bad track numbers", in fact when looking at a Track-Info with side 1 (instead of 0), track and side are correct in Track-Info but side is not ok in Sector-Info, normaly track/side are ignored in Sector-Info (Track-Info is used for that)... but still having the message, something else seems also wrong.
Do fix also message "Bad Command" while running a not existing file on disk.
Certainly linked to ''Orion Primes.dsk'' loading problem.
===== DSK: tapes =====
Do read .CDT files also.
I think @ralferoo had already written FPGA code for tape reading for his FPGA CPC. Maybe you can borrow some code from him?
Bryce.
Caprice32 has a nice tape.c implementation, in fact blocks are just read bit by bit (byte is shifted), at a certain speed. Perhaps starting with a fix CDT small file, reading blocks in loop, could be a nice approach around that.
Some has tryed reading sound directly (on emulator), switching to '1' when level (from 0.0 to 1.0) does pass over 0.5+0.1 and to '0' when level does pass below 0.5-0.1, that's the way @ralferoo uses, but @ralferoo seems also interested around CDT. ZX-Uno 464 is also using an audio jack input.
amstrad_190518_r005.8.16.8 does now read CDT. I've seen that sorgelig implements also the CDT with "Breaking Baud" demo running completely.
===== DSK: TODO : snapshoot purpose =====
Like in emulators, do something to go back in time while running a game.
For info, it seems called the "Multiface 2" purpose.
==== Transmit ====
Could be nice around cross-dev.
===== Transmit: TODO : Ethernet =====
Integration of "ethernec.v".
Several multiplayer games using several CPC does already exists : [[Virtual_Net_96]].
==== X/Y ====
===== X/Y: TODO : A X/Y input =====
I want to work also on screen-pen entry, is there a manner to detect an analog X/Y as pen or gun ? YES : [http://java.cpc-live.com/gx4000.php Markus Hohmann] does it, he implements the lightgun on JavaCPC-GX4000 using mouse :)
http://cpcrulez.fr/hardware-pistolet-magnum_light_phaser_ACPC.htm
register 11,12 and 13 ?
===== X/Y: Kempston mouse support =====
KLNHOMEALONE did ask AMX mouse - sorry about this, finally I added the Kempston mouse model only :p
Merge of Sorgelig kempston_mouse.v done in r005.8.16.6
[[File:Advanced art studio-kempston-mouse MiST.jpg|thumbnail|Advanced Art Studio - Kempston mouse]]
Advanced Art Studio > Misc.> Input Devices> Kempston mouse
Advanced Art Studio > Misc.> Input Devices> Fast cursor (if you want)
I do not like the AMX mouse, because it can trick a beginner: in fact, in Advanced Art Studio, even if the mouse is already moving, you have to activate the "AMX mouse" on "Misc" menu or else the mouse stay very very slow, the time you understand that our mouse is slow and that it's abnormal, you are disgusted with Advanced Art Studio.
=== Others tricks ===
