Changes
/* TODO : tapes */
In November 2014, I bought MiST-board, with two USB pro joysticks.
In September 2014, I bought NEXYS4, more powerfull than NEXYS2, with same external RAM, internal mini-sd, no PS/2 (it is a pmod option)... I have some patchs to make (MSB FAT32 offset). I would like to make a USB snifer sniffer also with it (usb to ethernet (wireshark))
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*'''30YMD.dsk''': in Benediction demo, at bottom some time you see some ghosts of central animation (too many HSync per screen ?)
*'''arkanoid2.dsk''': don't run in r005.8.13, but fine in r005.8.13e (experimental fork), ok in r005.8.14 (using default OSD value : MEM_WR=quick)
*'''trailblazer.dsk''': no more "raster" problem since r005.5, it's now perfect ! Palette heuristic offset (done for unlocking Batman Forever Demo) has a small effect in left (squares are not separated by a black line in first column) - same small defect in TV mode using r005.8.14.2... Thinking about a HSYNC offset of 2 (instead of 1 currently) then also delaying DATA+HDISP of 1 (char)
*'''imperial_mahjong.dsk''': modern EXA/EXA2 resolution not passing my color pallet heuristic :p
*'''rtypeee.dsk''': at begin of presentation, a draw of "jack plug" is done in a strange video mode, more than 200 pixels of height !, see [http://cpc.sylvestre.org/musee/musee_flipping_lace.html flipping lace]
==== perl FDC frame decoder ====
Adding a snifer sniffer into UPD765A.java :
writePort(int port, int value){System.out.println("writePort "+Util.hex((byte)port)+" "+Util.hex((byte)value));
readPort(int port) {
return data; // just before that
fdcMessages.pl
# perl fdcMessages.pl < test.dsk.snifersniffer.txt > test.snif.txt # perl fdcMessages.pl < orion.dsk.snifersniffer.txt > orion.snif.txt
use Switch;
my $param_count=0;my $data_read_count=0;my $data_write_count=0;my $result_count=0;
r005 : VGA 60H/TV 50Hz.
==== TODO DONE : A SCART output with border ====
Original output signal has no border, I have to implement the original border in TV mode.
Priority: HIGH! (asked by Markus Hohmann)
Done in r005.8.14.2
==== DONE : move SCART parameter into mist.ini ====
Done in r005.8.14.1
==== TODO DONE : refactor of Parrot PAL signal ====I found a running 15kHz TV, with [http://github.com/mist-devel/mist-board/blob/master/tutorials/soc/lesson11/lesson11.png mist-board tutorial lesson11 Parrot PAL] running fine, but not with my CoreAmstradr005.8.14.1. It's the same TV I used some years ago at festival with original CPC. I have to refactor Parrot tutorial and adapt it on CoreAmstrad in order to generate a better TV signal quality. Done in r005.8.14.2 In theory, simple_GateArrayInterrupt.vhd shall have : vsync_azrael<=etat_monitor_vhsync(2); hsync_azrael<=etat_monitor_hsync(2); if hSyncCount=2+4 thenIn practice - in r005.8.14.2 - here we have : vsync_azrael<=etat_monitor_vhsync(1); hsync_azrael<=etat_monitor_hsync(1); if hSyncCount=1+4 thenThis way screen is nicely centered but CPCWiki rule "The HSYNC is modified before being sent to the monitor. It happens 2us after the HSYNC from the CRTC and lasts 4us when HSYNC length is greater or equal to 6. If R2=46, and HSYNC width is 14 then monitor hsync starts at 48 and lasts until 51." is not respected. Test about centering screen are done using "BORDER 0", this way border is ignored and does interact with HSYNC/VSYNC screen synchronisation.
=== DONE : CRTC1 ===
=== TODO : AMX mouse support ===
Asked by KLNHOMEALONE.
=== TODO : pause Z80 while OSD is displayed ===
Cause playing Double Dragon II without "pause", is quite difficult.
Or else using "Pause" key ?
Can have border effect in sound (perhaps sound can be "freeze" and then still up...)
=== TODO : tapes ===
Do read .CDT files also.
I think @ralferoo had already written FPGA code for tape reading for his FPGA CPC. Maybe you can borrow some code from him?
Bryce.
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== Agile method ==
This project results of a an experiment applying Agile method.
Finally this project has taken 5 months. The result is a standalone platform that can run several games of Amstrad.
Normally, I had to dedicate 2 months on this project, but as result was so great, I continue to a standalone and better version.
===== State machine =====
Both component of Bootloader, it is to say SPI_MASTER and SDRAM_FAT32_LOADER components, does use several state-machinemachines, one state-machine per process, each process communicating with another one using "MASTER/SLAVE" : the master state-machine does ask a slave to do something, and slave does notify master when its task is finished.
Theses state-machine machines does use led debug : an integer contain contains the state of state machine, and this integer is displayed on 8 leds so you know where you are, it's for that I add several crash state states in order to understand why and where component does crash. In MiST-board, this is displayed on the five 7-segment I added in OSD, I add also a an input in order to select one or another state machine.
==== FPGAmstrad_amstrad_video schematic ====
The main component of this schematic is called aZRaEL_vram2vgaAmstradMiaow, due to my first experimentation about drawing a picture on VGA screen.
VGA display component does use the same parameters than unix '''modeline''' command, that's all you need, with that parameters you can display something on VGA at the frequency/resolution you choose.
[[File:aZRaEL_RAM_test_ok_zoom4_decal64_inv.jpg]]
RAM and VGA does not use the same frequency. I add between them a magical VRAM having two clock entries and solving this problem automatically.
The magic RAM in FPGA, getting two clock entries, is not as magical as I was thinking : in fact it does solve clock equations using the clock manager (DCM) and BUFG components (saying phase is freedom between input and output). If you want a set of clock clocks synchronized do not add a BUFG in one of its wires. If you don't care about synchronize of two clocks, just add it and then it will help to solve finer and greater the clock manager equations of DCM while compiling.
If you seem interested about strange clocks generated during last step of FPGA compile, do look after "time constraints file" and "timing closure".
===== Cut a wire, cut a function =====
When we cut a an input wire, we generally plug it to GND or Vcc.
For cutting a function, you have to insert a cut on it. A cut it's a return. You can insert a (very bad) forcing cut as:
==== Clock sequence : first try (prototype) ====
Original Gatearray of Amstrad is a sequencer (counter plugged with a clock), it manage manages synchronization between video card and z80 and memory access.
Historically there is a link between CU of CU/ALU, and... control bus and... how making your own sequencer. But I will say no more in order to not disturb these text part xD
Whatever, I made my own sequencer here in form of a bus of 4 wires called CLK4. CLK4 execute executes a simple repetitive sequence like 0001 0010 0011... CLK4(3), the last wire is directly connected to Z80 clock entry. Component Components not using explicit CLK4 as clock entry are generally using a not(CLK4(3)) entry, in order to do operation operations not as same time than z80.
Real Amstrad use uses buffer memory in front of each address and data access, and real z80 is clock low state active. Normally if you follow datasheet of z80 you know how to map memory following CU comportment. Or you do as Amstrad, saying that z80 CU sucks, I create my own sequencer, managing all my memories access, alternating CRTC work and z80 work with little synchronization, insert inserting by the way more pixels that can support my small CRTC...
How to use a sequence in VHDL :
==== Clock sequence : under time constraints (quality) ====
In fact, it's better to create you your clock sequencer wiring each CLK and not(CLK) directly from DCM, in this case you enter in time constraints norm, and then rules/checks are done on every _edge instruction. Choosing only one sort of _edge (rising or falling) seems better also. Using that way you just have more "bad compiling error" shown, helping you creating a better code (more stable/quality).
Clock sequence using a counter plugged with a clock was in fact a bad practice (but running fine in my first versions of FPGAmstrad as I'm a good blind developer), because output are not under clock constraint : just think about that a "not" component added just after a clock wire is a Time Constraints bad practice... destroying "time constraint" solver (the one telling you when your clock domains are bad (and why), "time constraint" is last step of FPGA compiling process, it is a an important step about quality, it shall be respected (generaly in a very last development effort, I shall say in a deploy effort))
==== Clock sequence : mirror VRAM (performance) ====
http://www.youtube.com/watch?v=fh4v4OXridc
USB is just a state machine (welcome how are you today, show me your state, show me your state, show me your state....), encoding (have to read USB manual), you can use some usb snifer software sniffer softwares to decode them(wireshark unix version does it fine). Snifer Sniffer software does not show low level message messages (ack ko ok) but does show the high level message messages (ones that show that a button is pressed or not)
As it is just encoding, you can capture signals and show that they differ only when you do unpress or press a button.
For reaching which wire you have to pull-up or pull-down, here the tips :
*For slave (ideal for sniffing) : just take your USB1 joystick without plug it, just supply it (+5v red, 0v black), and test while-black and green-black with voltmeter, if you have got 5v then put a VHDL pull-up, and if you have got 0v then put a VHDL pull-down.
*For master (ideal for creating a mini-host) : just take your PC USB1 port, and test whilewhite-black and green-black with voltmeter, if you have got 5v then put a VHDL pull-up, and if you have got 0v then put a VHDL pull-down. Normally you result two pull-down.
==== Synchronize, decode and check USB frames ====
One time sample is done, it is not readable. In fact USB frames are synchronized (they started with a certain synchronization pattern), encoded (NRZI), and checked (CRC). CRC type depends on frame length. Encoding is done for synchronization optimization.
Then using USB HID manual, you can understand type of frames, and author of them, and remark that the author alternatealternates: USB master (PC) or USB slave (joystick)
You can use some "USB sniffer software" in order to understand more easily some frames contain, but they generally don't give all frame, and full frame.
