Changes
/* Z80 architecture : T80_ALU.vhdl */
*'''split ink demo.dsk''': (from cpcrulez) : may help about ink raster calibration.
*'''Sultan's Maze.dsk''': does need the right part of keyboard (F0-F9 are used for directions in this game)
*'''Orion Primes.dsk''': does display "secteurs entrelacés" - "vérifiez votre copie", a FDC problem, perhaps "sectorId++" is not the good way to reach next sector, or else two tracks in one track.
*'''Batman_Forever.dsk''': some problem during flying chip demo part, and several rupture showing ghost lines around Vcc=0.
*'''30YMD.dsk''': in Benediction demo, at bottom some time you see some ghosts of central animation (too many HSync per screen ?)
[http://www.winape.net/download/plustest.zip WinAPE plustest.zip (including Instruction and Interrupt timing tests)]
===== Z80 architecture : T80.vhdl =====
17 pages of source codes to read.
Not analyzed yet completly.
Contains the main workflow of Z80: current MCycle and its current TState.
Contains T80_ALU.vhdl and T80_MCode.vhdl components.
===== Z80 architecture : T80_ALU.vhdl =====
6 pages of source codes to read.
Not analyzed yet completly. This analyse can certainly be wrong : wip.
Contains flags : C N P X H Y Z S
C : carry - set if result did not fit in the register
N : negative? - last instruction was substract
P : parity or overflow - overflow example : signed, 7F+7F=FE with overflow setted
X : undocumented
H : half carry - set if 4bit first bits of result did not fit in the register
Y : undocumented
Z : zero - set if result is zero
S : sign - it is an input ?
Contains ALU_Op : [ADD ADC SUB SBC AND XOR OR CP] ROT BIT [SET RES] DAA
ALU_Op is the basic instructions of Z80 coded here. T80_ALU.vhdl is a slave, a service exposed to T80_MCode.vhdl throw T80.vhdl
[[http://www.z80.info/decoding.htm § Disassembly tables]] shall make a cool ALU_Op quick reference card, doesn't it ?
===== Z80 architecture : T80_MCode.vhdl =====
First 5 pages, and last 2 pages of source codes to read. Others pages are "always the same" architectually speaking.
Not analyzed yet completly. This analyse can certainly be wrong : wip.
Gives instructions lengh : MCycles, TStates (please remark the 's' at end of theses words...), in [[http://www.zilog.com/docs/z80/um0080.pdf Z80 doc]] each instruction is timing described using "M Cycles" and "T States" vocabulary.
It's a "controler" (proof : you have some Set_*_To outputs), does gives orders to T80_ALU.vhdl throw T80.vhdl
Actions of this controler are :
* ALU_Op : the action !
* I_DJNZ I_CPL I_CCF I_SCF I_RETN I_BT I_BC I_BTR I_RLD I_RRD I_INRC : actions not for ALU (wiring input/ouput, changing flags...)
* Save_ALU/PreserveC : an option about register "erased or not" at next instruction
Instructions not coded in T80_MCode.vhdl but in T80.vhdl (strange, barbarian part of code ?) :
* Jump/E/XY Call RstP LDZ LDW LDSPHL Special_LD ExchangeDH/Dp/AF/RS
Inc_WZ register : take a look at [[http://www.righto.com/2014/10/how-z80s-registers-are-implemented-down.html § The WZ temporary registers]. It's a tmp internal register in fact.
=== Alignment of HSYNC Interrupt ===
Done in r005.8.14. Detected as CRTC0 by WakeUp! - "Enjoy the show" message displayed.
In r005.8.15. WakeUp! (CRTC0/MEM_wr quick) detected as Emu first time, and after a quick reset, does say detected as CRTC0.
==== DONE : CRTC1 detection ====
Integration of "ethernec.v".
=== TODO DONE : arnoldemu's testbench fdctest ===
arnoldemu's testbench to pass : test/fdctest/fdctest/fdctest.dsk
Have also to fix theses "Bad Command" responses from fdc (it seems that when you don't reach a track, you have to send back the current track instead of this "Bad Command" signal). Test : 30YMD demo, "disk change" message not running correctly, "another disk inserted" is not detected in this demo.
==== arnoldemu's testbench results ====
CoreAmstrad r005.8.15
* 27FAIL01/29FAIL01 : read_track6/read_track10 - very big sector size counter not implemented (more than 512B)
* 3DFAIL/45FREEZE : read_data_ov/test_write_ov - using flag simpleDSK.IS_ARNOLDEMU_TESTBENCH=false this test will fail/freeze in final version. It will not be implemented (does slow down some demos : 30YMD/Batman)
* 41FAIL06 : test_write2 - does corrupt the testbench itself (writing a deleted mark in testdisk.dsk file) using flag SDRAM_FAT32_LOADER.IS_ARNOLDEMU_TESTBENCH=false this test will pass in final version, one time :)
* 51FAIL02/52FAIL01 : bad5_cylinder/bad6_cylinder - writing data without data is not implemented
* 59FAIL01 format1 - format command not implemented
* 5EPASS : check_dtl3 - does pass but well to know that a dtl write less than sector_sector_size will not be taken into account (due to write per block of sdcard)
* 60FAIL01 : format2 - format command not implemented (this test is slow)
==== TODO : arnoldemu's second testbench ====
[http://www.cpctech.org.uk/test.zip http://www.cpctech.org.uk/test.zip] arnold test last update. Folder disc/, tests : "seek, recalibrate, sense interrupt status, sense drive status, write protect"
