Changes
/* Z80 architecture : T80_ALU.vhdl */
ALU_Op is the basic instructions of Z80 coded here. T80_ALU.vhdl is a slave, a service exposed to T80_MCode.vhdl throw T80.vhdl
[[http://www.z80.info/decoding.htm § Disassembly tables]] shall make a cool ALU_Op quick reference card, doesn't it ?
===== Z80 architecture : T80_MCode.vhdl =====
First 5 pages, and last 2 pages of source codes to read. Others pages are "always the same" architectually speaking.
Not analyzed yet completly. This analyse can certainly be wrong : wip.
Gives instruction instructions lengh : MCycles, TStates (please remark the 's' at end of theses words...), in [[http://www.zilog.com/docs/z80/um0080.pdf Z80 doc]] each instruction is timing described using "M Cycles" and "T States" vocabulary.
It's a "controler"(proof : you have some Set_*_To outputs), does gives orders to T80_ALU.vhdl throw T80.vhdl
Actions of this controler are :
Instructions not coded in T80_MCode.vhdl but in T80.vhdl (strange, barbarian part of code ?) :
* Jump/E/XY Call RstP LDZ LDW LDSPHL Special_LD ExchangeDH/Dp/AF/RS
Inc_WZ register : take a look at [[http://www.righto.com/2014/10/how-z80s-registers-are-implemented-down.html § The WZ temporary registers]. It's a tmp internal register in fact.
=== Alignment of HSYNC Interrupt ===
