Changes
/* Some bad instruction timing analyses */
===== Some bad instruction timing analyses =====
Based on [[http://www.winape.net/ WinAPE>download>Plus test>plustest.dsk]] testbench, mapped using [[http://clrhome.org/table/ Z80 instruction set - ClrHome]], instruction described then in [[http://www.zilog.com/docs/z80/um0080.pdf Z80 doc]], against [[http://www.winape.net/ WinAPE] passing testbench timing.
{| class====== "wikitable"|-! Hex !! Inst !! CPC timing !! MEM_wr:quick !! MEM_wr:slow !! remark|-| 02 || LD (BC),A ====== CPC timing: || 2; quick: || 2; low: || 3|| Normaly MEM_WR access is not prolongated. This instruction does certainly launch write since first step.====== |-| 10 || || 4/3 || 4/2 || 4/2|-| 12 || || 2 || || 3|-| 22 || || 5 || ? || 6|-| 2A || LD HL,(nn) ====== CPC timing: || 5; quick: || 4; low: || 4|| In fact this instruction does launch two MEM_WR, and shall be prolongated two times.|-| 32 || || 4 || || 5|-| 34 || || 3 || || 4|-| 35 || || 3 || || 4|-| 36 || || 3 || || 4|-| 70 || || 2 || || 3|-| 71 || || 2 || || 3|-| 72 || || 2 || || 3|-| 73 || || 2 || || 3|-| 74 || || 2 || || 3|-| 75 || || 2 || || 3|-| 77 || || 2 || || 3|-| C0 || || 2/4 || 2/3 || 2/3|-| C4 || || 3/5 || || 3/6|-| C5 || || 4 || 3 || 4|-| C7 || || 4 || 3 || 3|-| C8 || || 4/2 || 3/2 || 3/2|-| CC || || 5/3 || 5/3 || 6/3|-| CD || || 5 || || 6|-| CF || || 4 || 3 || 3|-| D0 || || 2/4 || 2/3 || 2/3|}
===== Some bad instruction analyses =====
Based on [[https://cpcrulez.fr/applications_CPM-util-zexall.htm Zexall: Z80 instruction set exerciser]], running fine in JavaCPC.
