Changes
/* RET cc and WAIT_n timing analysis */
Normaly, without WAIT_n generator (even modulo 4), NOP should take 1 M-cycles and 4 T-states, so this instruction should pass using plustest.dsk at 0x00. Does fail here.
In r005.6, cpctest.dsk did pass. Have to do somes experiments from it. Removing MEM_wr:slow both test tests does still run fine (NOP/HALT (x00 x76)). Removing full mod4 WAIT_n generator, cpctest.dsk and plustest.dsk does fail. So NOP has to be synchronized (plustest.dsk is full of NOPs)
=== Test of a real Zilog 80 ===
