Changes
/* VRAM to VGA (aZRaEL_vram2vgaAmstradMiaow) */
RAM and VGA does not use the same frequency. I add between them a magical VRAM having two clock entries and solving this problem automatically.
The magic RAM in FPGA, getting two clock entry, is not as magical as I thinked : it does solve clock equations using the clock manager (DCM) and BUFG components (saying phase is freedom between input and output). If you want a set of clock synchronized do not add a BUFG in one of its wires. If you don't care about synchronize of two clocks, just add it and then it will help to solve finer and greater the clock manager equations of DCM while compilatingcompiling.
=== Alignment of HSYNC Interrupt ===
