Changes
/* Interrupt service (Vectored interrupts) */ - Bit 0 tested, never set in IM0
The ASIC can produce interrupts from four sources: the raster interrupt and the three sound generator "DMA" channels. The ASIC will always supply a vector which can be used by the CPU in interrupt modes 0 and 2 or ignored in interrupt mode 1.
The top 5 bits of the vector will be supplied from bit D7-D3 of a memory mapped interrupt vector register (IVR) at address 6805h in the ASIC, and the next two bits will determine the source of the interrupt. Bit D0 of the vector supplied is ignored by the Z80 in interrupt mode 2, but may be used in interrupt mode 0 (???)always zero.
<pre>
D2 D1 D0 0 0 0 DMA channel 2 interrupt vector 0 1 0 DMA channel 1 interrupt vector 1 0 0 DMA channel 0 interrupt vector 1 1 0 Raster interrupt vector
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The value written to bit D0 of the IVR controls whether DMA channel interrupts are automatically cleared, but has no effect on the vector itself (???). The contents of register 6805h are undefined at reset except that bit D0 will be set to 1. Software should always set up the IVR before placing the CPU in vectored interrupt mode.
The interrupts are prioritized in a fixed sequence. The raster interrupt has the highest priority, followed by DMA channels 2 down to 0 respectively. For compatibility with earlier models, the raster interrupt is reset either by a CPU interrupt acknowledge cycle, or by writing a 1 to bit D4 of the mode and ROM enable register. The sound channel interrupts are cleared by writing a 1 to the relevant bit in the DCSR. To simplify vectored interrupt systems, they may also be cleared automatically by a CPU interrupt acknowledge cycle. This feature is enabled by writing a 0 to bit D0 of IVR.
