Changes

Gate Array

In the CPC+ system, the functions of the Gate-Array are integrated into The gate array is a single ASIC. When the ASIC is "locked", the extra features are not available and the ASIC operates the same as the Gate-Array specially designed chip exclusively for use in the Amstrad CPC allowing programs written for the CPC to work on the Plus without modification. The ASIC must be "un-locked" to access the new featuresand was designed by Amstrad plc.

In the KC compact CPC+ system, the functions of the Gate-Array are integrated into a single [[ASIC|ASIC]]. When the ASIC is "emulatedlocked" in TTL logic , the extra features are not available and by the Zilog Z8536 CIOASIC operates the same as the Gate-Array in the CPC allowing programs written for the CPC to work on the Plus without modification. The ASIC must be "un-locked" to access the new features.

In the "cost-down" version of the CPC6128[[KC Compact]] system, the functions of the Gate-Array are integrated into a ASIC"emulated" in TTL chips, [[CIO Overview|CIO]], and its color translation EPROM.

The In the "cost-down" version of the CPC6128, the functions of the Gate -Array is described here, as it is in are integrated into a standard CPCASIC.

== Controlling the The Gate Array ==is responsible for the display (colour palette, resolution, horizontal and vertical sync), interrupt generation and memory arrangement.

The gate array is controlled by I/O. The gate array is selected when bit 15 of == Controlling the I/O port address is set to "0" and bit 14 of the I/O port address is set to "1". The values of the other bits are ignored. However, to avoid conflict with other devices in the system, these bits should be set to "1".Gate Array ==

The recommended gate array is controlled by I/O. The gate array is selected when bit 15 of the I/O port address is set to "0" and bit 14 of the I/O port address is &7Fxxset to "1". The values of the other bits are ignored. However, to avoid conflict with other devices in the system, these bits should be set to "1".

The function to be performed recommended I/O port address is selected by writing data to the Gate-Array, bit 7 and 6 of the data define the function selected (see table below). It is not possible to read from the Gate-Array&7Fxx.

Bit The function to be performed is selected by writing data to the Gate-Array, bit 7 Bit and 6 Functionof the data define the function selected (see table below). It is not possible to read from the Gate-Array.

{|{{Prettytable|width: 700px; font-size: 2em;}}|-|''Data Bit 7''||''Data Bit 6''||''Function''|-| 0 || 0 || Select pen|-| 0 || 1 || Select colour for selected pen|-| 1 1 || 0 || Select screen mode, rom ROM configuration and interrupt control|-| 1 || 1 Ram || RAM Memory Management (note 1)|-|}

===== Note =====

This function is not available in the Gate-Array, but is performed by a device at the same I/O port address location. In the CPC464,CPC664 and KC compact, this function is performed in a memory-expansion (e.g. Dk'Tronics 64K Ram RAM Expansion), if this expansion is not present then the function is not available. In the CPC6128, this function is performed by a [[PAL16L8|PAL ]] located on the main PCB, or a memory-expansion. In the 464+ and 6128+ this function is performed by the ASIC or a memory expansion. Please read the document on Ram Management RAM management for more information. <br>Pen selection<br>When bit 7 and bit 6 are set to "0", the remaining bits determine which pen is to have its colour changed. When bit 4 is set to "0", bits 3 to 0 define which pen is to be selected. When bit 4 is set to "1", the value contained in bits 3-0 is ignored and the border is selected.

Each mode has a fixed number of pensWhen bit 7 and bit 6 are set to "0", the remaining bits determine which pen is to have its colour changed. Mode When bit 4 is set to "0 has 16 pens", mode 1 has bits 3 to 0 define which pen is to be selected. When bit 4 pens is set to "1", the value contained in bits 3-0 is ignored and mode 2 has 2 pensthe border is selected.

Bit Value Function <br>7 Each mode has a fixed number of pens. Mode 0 Gate Array function "Pen Selection" <br>6 0 <br>5 x not used <br>has 16 pens, mode 1 has 4 0 Select pen <br>3 x Pen Number <br>pens and mode 2 x <br>1 x <br>0 xhas 2 pens.

Summary<br>Bit Value Function <br>7 0 Gate Array function "Colour Selection" <br>6 1 <br>5 x not used <br>4 x Colour number <br>3 x <br>2 x <br>1 x <br>0 x

<br>Hardware colour palette{|{{Prettytable|width:700px; font-size: 2em;}}|-| ''Bit'' || ''Value'' || ''Function''|-| 7 || 0 || rowspan="2" | Gate Array function "Pen Selection"|-| 6 || 0|-| 5 || - || not used|-| 4 || 0 || Select pen|-| 3 || x || rowspan="4" | Pen number|-| 2 || x|-| 1 || x|-| 0 || x|}

Colour Number Colour Name <br>0 White <br>== Register 1 White - Palette Data (note 1) <br>2 Sea Green <br>3 Pastel Yellow <br>4 Blue <br>5 Purple <br>6 Cyan <br>7 Pink <br>8 Purple (note 1) <br>9 Pastel Yellow (note 1) <br>10 Bright Yellow <br>11 Bright White <br>12 Bright Red <br>13 Bright Magenta <br>14 Orange <br>15 Pastel Magenta <br>16 Blue (note 1) <br>17 Sea Green (note 1Colour selection) <br>18 Bright Green <br>19 Bright Cyan <br>20 Black <br>21 Bright Blue <br>22 Green <br>23 Sky Blue <br>24 Magenta <br>25 Pastel Green <br>26 Lime <br>27 Pastel Cyan <br>28 Red <br>29 Mauve <br>30 Yellow <br>31 Pastel Blue==

This Even though there is not an official provision for 32 colours, only 27 are possible. The remaining colours are duplicates of those already in the colour palette.

Screen == Register 2 - Select screen mode selectionand ROM configuration ==

The function of bits 1 and 0 This is to define a general purpose register responsible for the [[Video modes|screen mode. The settings for bits 1 ]] and 0 and the corresponding screen mode are given in the table belowROM configuration.

Bit 1 Bit 0 === Screen mode0 0 Mode 0, 160x200 resolution, 16 colours <br>0 1 Mode 1, 320x200 resolution, 4 colours <br>1 0 Mode 2, 640x200 resolution, 2 colours <br>1 1 Mode 3, 160x200 resolution, 4 colours (note 1)selection ===

<br>This mode is not official. From the combinations possible, we can see that 4 modes can be defined, although the Amstrad only has 3. Mode 3 is similar to mode The function of bits 1 and 0, because it has the same resolution, but it is limited to only 4 colours. <br>Mode changing is synchronised with HSYNC. If define the screen mode is changed, it will take effect from the next HSYNC. <br>Rom configuration selection<br>Bit 2 is used to enable or disable the lower rom area. The lower rom area occupies memory addressess &amp;0000-&amp;3fff settings for bits 1 and 0 and is used to access the operating system rom. When the lower rom area is is enabled, reading from &amp;0000-&amp;3FFF will return data in the rom. When a value is written to &amp;0000-&amp;3FFF, it will be written to the ram underneath the rom. When it is disabled, data read from &amp;0000-&amp;3FFF will return the data corresponding screen mode are given in the ramtable below.

Similarly, bit 3 controls enabling or disabling of the upper rom area. The upper rom area occupies memory addressess &amp{|{{Prettytable|width: 700px;C000font-&ampsize: 2em;FFFF and is BASIC or any expansion roms which may be plugged into a rom board/box. See the document on upper rom selection for more details. When the upper rom area enabled}}|-| ''Bit 1'' || ''Bit 0'' || ''Screen mode''|-| 0 || 0 || Mode 0, reading from &amp;c000160x200 resolution, 16 colours|-&amp;ffff| 0 || 1 || Mode 1, will return data in the rom. When data is written to &amp;c000320x200 resolution, 4 colours|-&amp;FFFF| 1 || 0 || Mode 2, it will be written to the ram at the same address as the rom. When the upper rom area is disabled640x200 resolution, and data is read from &amp;c0002 colours|-&amp;ffff the data returned will be the data in the ram.| 1 || 1 || Mode 3, 160x200 resolution, 4 colours (undocumented)|}

Bit 4 controls the interrupt generation* Mode 3 is not official. It From the combinations possible, we can see that 4 modes can be used defined, although the Amstrad only has 3. Mode 3 is similar to delay interruptsmode 0, because it has the same resolution, but it is limited to only 4 colours. See Mode 3 is not supported by the document on interrupt generation for more information[[KC Compact]] (which outputs black in Mode 3).

Summary<br>Bit Value Function <br>7 0 Gate Array function <br>6 1 <br>5 x not used <br>4 x Interrupt generation control <br>3 1 Upper rom area disable <br>0 Upper rom area enable <br>2 1 Lower rom area disable <br>0 Lower rom area enable <br>1 x Mode selection <br>0 xchanging is synchronised with HSYNC. If the mode is changed, it will take effect from the next HSYNC.

== Programming Similarly, bit 3 controls enabling or disabling of the Gate Array upper ROM area. The upper ROM area occupies memory addressess &amp;C000- Examples ==&amp;FFFF and is BASIC or any expansion ROMs which may be plugged into a ROM board/box. See the document on [[Upper ROM Bank Number|upper rom selection]] for more details. When the upper ROM area enabled, reading from &amp;c000-&amp;ffff, will return data in the ROM. When data is written to &amp;c000-&amp;FFFF, it will be written to the RAM at the same address as the ROM. When the upper ROM area is disabled, and data is read from &amp;c000-&amp;ffff it will be the data in the RAM.

Defining Bit 4 controls the colours, <br>Setting pen 0 interrupt generation. It can be used to Bright Whitedelay interrupts. See the document on interrupt generation for more information.

=== Summary === {|{{Prettytable|width: 700px; font-size: 2em;}}|-| ''Bit'' || ''Value'' || ''Function''|-| 7 || 1 || rowspan="2" | Gate Array function|-| 6 || 0 |-| 5 || - || not used|-| 4 || x || Interrupt generation control|-| 3 || x || 1=Upper ROM area disable, 0=Upper ROM area enable|-| 2 || x || 1=Lower ROM area disable, 0=Lower ROM area enable|-| 1 || x || rowspan="2" | Screen Mode slection|-| 0 || x|} == Register 3 - RAM Banking == This register exists only in CPCs with 128K RAM (like the CPC 6128, or CPCs with [[Standard Memory Expansions]]). Note: In the CPC 6128, the register is a separate [[PAL16L8|PAL]] that assists the Gate Array chip. {|{{Prettytable|width: 700px; font-size: 2em;}}|-| ''Bit'' || ''Value'' || ''Function''|-| 7 || 1 || rowspan="2" | Gate Array function 3|-| 6 || 1 |-| 5 || b || rowspan="3" |64K bank number (0..7); always 0 on an unexpanded CPC6128, 0-7 on [[Standard Memory Expansions]]|-| 4 || b|-| 3 || b|-| 2 || x || rowspan="3" | RAM Config (0..7)|-| 1 || x|-| 0 || x|}  The 3bit RAM Config value is used to access the second 64K of the total 128K RAM that is built into the CPC 6128 or the additional 64K-512K of standard memory expansions. These contain up to eight 64K ram banks, which are selected with bit 3-5. A standard CPC 6128 only contains bank 0. Normally the register is set to 0, so that only the first 64K RAM are used (identical to the CPC 464 and 664 models). The register can be used to select between the following eight predefined configurations only:  -Address- 0 1 2 3 4 5 6 7 0000-3FFF RAM_0 RAM_0 '''RAM_4''' RAM_0 RAM_0 RAM_0 RAM_0 RAM_0 4000-7FFF RAM_1 RAM_1 '''RAM_5''' '''RAM_3''' '''RAM_4''' '''RAM_5''' '''RAM_6''' '''RAM_7''' 8000-BFFF RAM_2 RAM_2 '''RAM_6''' RAM_2 RAM_2 RAM_2 RAM_2 RAM_2 C000-FFFF RAM_3 '''RAM_7''' '''RAM_7''' '''RAM_7''' RAM_3 RAM_3 RAM_3 RAM_3 The Video RAM is always located in the first 64K, VRAM is in no way affected by this register. == Programming the Gate Array - Examples == Defining the colours, <prebr>Setting pen 0 to Bright White. <pre>LD BC,7F00 &nbsp;;Gate Array portLD A,%00000000+0 &nbsp;;Pen number (and Gate Array function)OUT (C),A &nbsp;;Send pen numberLD A,%01000000+11 &nbsp;;Pen colour (and Gate Array function)OUT (C),A &nbsp;;Send it

Setting the mode and rom ROM configuration, Mode 2, upper and lower rom ROM disabled.

LD BC,7F00 &nbsp;;Gate array portLD A,%10000000+%00001110 &nbsp;;Mode and rom ROM selection (and Gate Array function)OUT (C),A &nbsp;;Send it

<br>conversion chart<br>=== Misc === The hardware colour number is different to the colour range used by the firmware, so a conversion chart is provided for the corresponding firmware/hardware colour values and the corresponding colour name. === Note === The firmware keeps track of the colours it is using. Every VSYNC (assuming interrupts are enabled) the firmware sets the colours. This enables the user to have flashing colours. If the user selects a new colour using the gate array, the new colour will flash temporarily and then return to its original colour. This is due to the firmware resetting the colour. When using the firmware, use its routines to select the colour, and the colour will remain. Example: [For whatever reason, this example does NOT refer to the above firmware stuff]<pre>ld bc,7f00+1&nbsp;;Gate array function (set pen);and pen numberout (c),cld bc,7f00&nbsp;;41 ;Gate array function (set colour);and colour numberout (c),cret</pre> == Palette R,G,B definitions == There are 27 colours which are generated from red, green and blue mixed in different quantities. There are 3 levels of red, 3 levels of green and 3 levels of blue, and these can be thought of as off/no colour, half-on/half-colour, and on/full-colour.  To display a CPC image you will need to use a analogue monitor with a composite sync.  === Palette sorted by Hardware Colour Numbers === {| class="FCK__ShowTableBorders"|-| ''Hardware Number||Firmware Number|| ''Colour Name'' | ''R&nbsp;%'' || ''G&nbsp;%'' || ''B&nbsp;%'' || ''Colour''|-| 0 (40h) || 13 || White || 50|| 50|| 50|| bgcolor="#808080" | |-| 1 (41h) || (13) || White || 50|| 50|| 50|| bgcolor="#808080" | |-| 2 (42h) || 19 || Sea Green || 0||100|| 50|| bgcolor="#00ff80" | |-| 3 (43h) || 25 || Pastel Yellow ||100||100|| 50|| bgcolor="#ffff80" | |-| 4 (44h) || 1 || Blue || 0|| 0|| 50|| bgcolor="#000080" | |-| 5 (45h) || 7 || Purple ||100|| 0|| 50|| bgcolor="#ff0080" ||-| 6 (46h) || 10 || Cyan || 0|| 50|| 50|| bgcolor="#008080" | |-| 7 (47h) || 16 || Pink ||100|| 50|| 50|| bgcolor="#ff8080" | |-| 8 (48h) || (7) || Purple ||100|| 0|| 50|| bgcolor="#ff0080" | |-| 9 (49h) || (25) || Pastel Yellow ||100||100|| 50|| bgcolor="#ffff80" | |-| 10 (4Ah) || 24 || Bright Yellow ||100||100|| 0|| bgcolor="#ffff00" | |-| 11 (4Bh) || 26 || Bright White ||100||100||100|| bgcolor="#ffffff" | |-| 12 (4Ch) || 6 || Bright Red ||100|| 0|| 0|| bgcolor="#ff0000" | |-| 13 (4Dh) || 8 || Bright Magenta||100|| 0||100|| bgcolor="#ff00ff" | |-| 14 (4Eh) || 15 || Orange ||100|| 50|| 0|| bgcolor="#ff8000" | |-| 15 (4Fh) || 17 || Pastel Magenta||100|| 50||100|| bgcolor="#ff80ff" | |-| 16 (50h) || (1) || Blue || 0|| 0|| 50|| bgcolor="#000080" | |-| 17 (51h) || (19) || Sea Green || 0||100|| 50|| bgcolor="#00ff80" | |-| 18 (52h) || 18 || Bright Green || 0||100|| 0|| bgcolor="#00ff00" | |-| 19 (53h) || 20 || Bright Cyan || 0||100||100|| bgcolor="#00ffff" | |-| 20 (54h) || 0 || Black || 0|| 0|| 0|| bgcolor="#000000" ||-| 21 (55h) || 2 || Bright Blue || 0|| 0||100|| bgcolor="#0000ff" | |-| 22 (56h) || 9 || Green || 0|| 50|| 0|| bgcolor="#008000" | |-| 23 (57h) || 11 || Sky Blue || 0|| 50||100|| bgcolor="#0080ff" | |-| 24 (58h) || 4 || Magenta || 50|| 0|| 50|| bgcolor="#800080" | |-| 25 (59h) || 22 || Pastel Green || 50||100|| 50|| bgcolor="#80ff80" | |-| 26 (5Ah) || 21 || Lime || 50||100|| 0|| bgcolor="#80ff00" | |-| 27 (5Bh) || 23 || Pastel Cyan || 50||100||100|| bgcolor="#80ffff" | |-| 28 (5Ch) || 3 || Red || 50|| 0|| 0|| bgcolor="#800000" | |-| 29 (5Dh) || 5 || Mauve || 50|| 0||100|| bgcolor="#8000ff" | |-| 30 (5Eh) || 12 || Yellow || 50|| 50|| 0|| bgcolor="#808000" | |-| 31 (5Fh) || 14 || Pastel Blue || 50|| 50||100|| bgcolor="#8080ff" | |} === Palette sorted by Firmware Colour Numbers === {| class="FCK__ShowTableBorders"|-| ''Firmware Number'' || ''Hardware Number'' || ''Colour Name'' | ''R&nbsp;%'' || ''G&nbsp;%'' || ''B&nbsp;%'' || ''Colour''|-| 0|| 54h ||Black || 0|| 0|| 0||bgcolor="#000000"||-| 1|| 44h (or 50h) ||Blue || 0|| 0|| 50||bgcolor="#000080"||-| 2|| 55h ||Bright Blue || 0|| 0||100||bgcolor="#0000ff"||-| 3|| 5Ch ||Red || 50|| 0|| 0||bgcolor="#800000"||-| 4|| 58h ||Magenta || 50|| 0|| 50||bgcolor="#800080"||-| 5|| 5Dh ||Mauve || 50|| 0||100||bgcolor="#8000ff"||-| 6|| 4Ch ||Bright Red ||100|| 0|| 0||bgcolor="#ff0000"||-| 7|| 45h (or 48h) ||Purple ||100|| 0|| 50||bgcolor="#ff0080"||-| 8|| 4Dh ||Bright Magenta ||100|| 0||100||bgcolor="#ff00ff"||-| 9|| 56h ||Green || 0|| 50|| 0||bgcolor="#008000"||-|10|| 46h ||Cyan || 0|| 50|| 50||bgcolor="#008080"||-|11|| 57h ||Sky Blue || 0|| 50||100||bgcolor="#0080ff"||-|12|| 5Eh ||Yellow || 50|| 50|| 0||bgcolor="#808000"||-|13|| 40h (or 41h) ||White || 50|| 50|| 50||bgcolor="#808080"||-|14|| 5Fh ||Pastel Blue || 50|| 50||100||bgcolor="#8080ff"||-|15|| 4Eh ||Orange ||100|| 50|| 0||bgcolor="#ff8000"||-|16|| 47h ||Pink ||100|| 50|| 50||bgcolor="#ff8080"||-|17|| 4Fh ||Pastel Magenta ||100|| 50||100||bgcolor="#ff80ff"||-|18|| 52h ||Bright Green || 0||100|| 0||bgcolor="#00ff00"||-|19|| 42h (or 51h) ||Sea Green || 0||100|| 50||bgcolor="#00ff80"||-|20|| 53h ||Bright Cyan || 0||100||100||bgcolor="#00ffff"||-|21|| 5Ah ||Lime || 50||100|| 0||bgcolor="#80ff00"||-|22|| 59h ||Pastel Green || 50||100|| 50||bgcolor="#80ff80"||-|23|| 5Bh ||Pastel Cyan || 50||100||100||bgcolor="#80ffff"||-|24|| 4Ah ||Bright Yellow ||100||100|| 0||bgcolor="#ffff00"||-|25|| 43h (or 49h) ||Pastel Yellow ||100||100|| 50||bgcolor="#ffff80"||-|26|| 4Bh ||Bright White ||100||100||100||bgcolor="#ffffff"||} === Intensities === The 0%, 50%, and 100% values in the above tables are "should-be" values. However, the real hardware doesn't exactly match that intensities. The actual intensities depend on the luminance mixing (R,G,B tied together via resistors), on chipset (classic CPC, or newer ASIC ones), and on the load applied by external hardware (Monitor, or TV set).* [[CPC Palette]] - some more details === To calculate the colour value === '''Red'''  0% =&gt; do not add anything  50% =&gt; add 3  100% =&gt; add 6  '''Green'''  0% =&gt; do not add anything  50% =&gt; add 9  100% =&gt; add 18

The firmware keeps track of the colours it is using. Every VSYNC (assuming interrupts are enabled) the firmware sets the colours. This enables the user to have flashing colours. If the user selects a new colour using the gate array, the new colour will flash temporarily and then return to it's original colour. This is due to the firmware re- setting the colour. When using the firmware, use it's routines to select the colour, and the colour will remain. <br>Firmware Colour Number Colour Name Hardware Colour Number Quick reference hardware colour select value <br>0 Black 20 % =&ampgt;54 <br>1 Blue 4 &amp;44 <br>2 Bright Blue 21 &amp;55 <br>3 Red 28 &amp;5C <br>4 Magenta 24 &amp;58 <br>5 Mauve 29 &amp;5D <br>6 Bright Red 12 &amp;4C <br>7 Purple 5 &amp;45 <br>8 Bright Magenta 13 &amp;4D <br>9 Green 22 &amp;56 <br>10 Cyan 6 &amp;46 <br>11 Sky Blue 23 &amp;57 <br>12 Yellow 30 &amp;5E <br>13 White 0 &amp;40 <br>14 Pastel Blue 31 &amp;5F <br>15 Orange 14 &amp;4E <br>16 Pink 7 &amp;47 <br>17 Pastel Magenta 15 &amp;4F <br>18 Bright Green 18 &amp;52 <br>19 Sea Green 2 &amp;42 <br>20 Bright Cyan 19 &amp;53 <br>21 Lime 26 &amp;5A <br>22 Pastel Green 25 &amp;59 <br>23 Pastel Cyan 27 &amp;5B <br>24 Bright Yellow 10 &amp;4A <br>25 Pastel Yellow 3 &amp;43 <br>26 Bright White 11 &amp;4Bdo not add anything

Pallette R,G,B definitions<brgallery>There are 27 colours which are generated from red, green and blue mixed in different quantitiesImage:40010_am2_metal. There are 3 levels of red, 3 levels of green and 3 levels of blue, and these can be thought of as off/no colour, half-on/half-colour, and on/full-colourjpg|40010 GA Metal LayerImage:40010_am2_acid.jpg|40010 GA with Metal Layer removedImage:40226_am4_metal.jpg|40226 PreASIC Metal Layer</gallery>

This table shows the relationship between hardware colour number, colour name *[[Gate Array and RGB mixing.ASIC Pin-Outs]]

<br>RGB assignments for the software colours<br>This is simply a sidenote to illustrate a pattern in the RGB assignments of the software colours and to show how their value is calculated*[[Media:40010-simplified V03. Firmware Colour Number Colour Name R % G % B % <br>0 Black 0 0 0 <br>1 Blue 0 0 50 <br>2 Bright Blue 0 0 100 <br>3 Red 50 0 0 <br>4 Magenta 50 0 50 <br>5 Mauve 50 0 100 <br>6 Bright Red 100 0 0 <br>7 Purple 100 0 50 <br>8 Bright Magenta 100 0 100 <br>9 Green 0 50 0 <br>10 Cyan 0 50 50 <br>11 Sky Blue 0 50 100 <br>12 Yellow 50 50 0 <br>13 White 50 50 50 <br>14 Pastel Blue 50 50 100 <br>15 Orange 100 50 0 <br>16 Pink 100 50 50 <br>17 Pastel Magenta 100 50 100 <br>18 Bright Green 0 100 0 <br>19 Sea Green 0 100 50 <br>20 Bright Cyan 0 100 100 <br>21 Lime 50 100 0 <br>22 Pastel Green 50 100 50 <br>23 Pastel Cyan 50 100 100 <br>24 Bright Yellow 100 100 0 <br>25 Pastel Yellow 100 100 50 <br>26 Bright White 100 100 100 <br>To calculate the colour valuepdf]] [https: <br>Red <br>0% =&gt; do not add anything <br>50% =&gt; add 3 <br>100% =&gt; add 6 <br>Green <br>0% =&gt; do not add anything <br>50% =&gt; add 9 <br>100% =&gt; add 18 <br>Blue <br>0% =&gt; do not add anything <br>50% =&gt; add 1 <br>100% =&gt; add 2//www.cpcwiki.eu/forum/amstrad-cpc-hardware/gate-array-decapped!/msg170713/#msg170713 Forum thread] Gate Array schematics - reverse engineered by Gerald

<br>Green Screen Colours<br>On a green screen (where all colours are shades of green), the colours (in the software== External links ==* [https:/firmware colours), are in order of increasing intensity/www. So that black is very dark, and white is bright green, and colour 13 is a medium greengrimware. org/doku.php/documentations/devices/gatearray Gate Array documentation from Grimware]* [http://quasar.cpcscene.net/doku.php?id=assem:gate_array Quasar Gate Array documentation (Thanks to Mark Rison for this informationin french) <br>]

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