Amstrad Plus 6128 - memory mapping while ASIC is paged in

[eto]

I was thinking about an internal RAM upgrade for the GX4000 to 128KB which won't require the soldering. I'm trying to understand the RAM access of a 6128plus while the ASIC is paged in and I am wondering what exactly is happening while the ASIC is paged in. Unfortunately I couldn't find a clear answer yet, but maybe someone can help.


1) while ASIC is paged in at &4000-&7fff, not all addresses will be used by the ASIC. Will writes to/reads from the unused addresses go to RAM instead? If not, what happens in that case? Nothing at all?

2) if ASIC is paged in and also 6128 RAM banking is active, will RAM reads/writes to &4000-&7fff go to the ASIC or to the RAM? I would expect it's going to the ASIC...

3) in case it's always just ASIC: how does the ASIC prevent RAM from being accessed? Is there a kind of logic like RAMDIS in the CPC that disconnects RAM? Or will it just not send the CAS signal to the RAM, so the RAM won't put data to the bus/read from the bus?

[TotO]

See RMR2: https://www.grimware.org/doku.php/documentations/devices/gatearray