Banked Video RAM?

[zhulien]

I was thinking we have banked ROM, banked CPU RAM, banked Multifaceted 2 RAM, banked Rombo VIDI RAM...

if we were to implement banked Video RAM in the CPC, would that be hard and what could we get out of the current CRTC with more RAM?

I have a couple of thoughts... similar to some hardware tricks on CPC, if we have banked 16k chunks then some existing effects could have the benefit of more region data available... is there much practical use in this?  

I might be wrong but my understanding currently is we can use 64k RAM currently from CRTC but only in blocks of 32k.  If our software is loaded into #C2 we would have a full 64k CPU RAM in addition to a full 64k CRTC RAM.  we do have some complicated programming running in #C2 mode to access additional ram (C4, c5, c6, c7) without disrupting the video display.

On a 6128 plus we could have 32k CRTC RAM, hardware sprites and DMA Audio RAM with our software mostly in #c2... a good organisation for games.

I really want a good video card for CPC that ideally let's us bank the video RAM for data transfers, but compatible with VGA even if it were like a PAL overseas resolution.  On paper the simplest appears to be existing CPC hardware with some type of scan doubler... but perhaps more can be achievable without much expense so everyone doesn't have the it is too expensive excuse.

[Bryce]

I'm probably the wrong person to answer this, but the video RAM is banked. ie: you can change which chunk of RAM the CRTC mapped to. However, it is in 16K chunks and they are directly mapped to the screen area.

Bryce.

[McArti0]

What do You want more?

https://www.cpcwiki.eu/forum/programming/256x256-in-mode-0-1024x51225hz-overscan-and-65kb-vram-for-basic-it-s-coming!/msg215472/#msg215472

Write to video RAM bank 3 is at C3 setting (0,3,2,7) and to RAM bank 1 is  at C1 setting (0,1,2,7)

Using the whole bank 0 for video is problematic because in address 0038 there is a jump to the interrupt routine. When you write to the bank 0 these 3 bytes are visible on the screen.

ps. CRTC R12=&xC and we have 32kB screen without interrupt. With interrupt we have 64kB Screen.

[andycadley]

What are you hoping to accomplish? As you say yourself, you can page all of the CRTC accessible RAM out by using the #C2 paging configuration. Other than that, there isn't really a benefit to paging as such. 

You can't get a better screen resolution or more colours or anything like that simply because there is 64K of memory present, the hardware just doesn't work like that.

[McArti0]

You can't get a better screen resolution or more colours or anything like that simply because there is 64K of memory present, the hardware just doesn't work like that.

Play Pinball Dreem..
Scroll in 64kb space video ram.
Two pages overscan. ~60 flikering colors.

My 1024x480 resolution. On LCD

[Prodatron]

Of course I would like to have a CRTC, which can use RAM from the second 64K of the 6128 as well: Like on the Amstrad PCW or the Enterprise 128.

Unfortunately that's not possible on the CPC, so wie have to live with this. While demos and some games use a maximum of 48K there are already several examples which are using the full first 64K as VRAM.

[McArti0]

I know how to add vram to CRTC in CPC6128 and change bank64-0 to bank64-1.

We need to add an adapter under PAL/GAL 40030.

Instruction e.g. 2xfast OUT &7FFF,xb11xxxxxx will be to change CAS0 and CAS1 signal and thats all.

We have to call this mod SuperHiperVRAM and that's it.

GAL has 3 other NA pins. CRTC can use other 3*64kb (sumarry 256kB VRAM).

To add other VRAM, we need an adapter for one RAM memory.

[HAL6128]

Adapter?

[GUNHED]

Of course I would like to have a CRTC, which can use RAM from the second 64K of the 6128 as well: Like on the Amstrad PCW or the Enterprise 128.

Unfortunately that's not possible on the CPC, so wie have to live with this. While demos and some games use a maximum of 48K there are already several examples which are using the full first 64K as VRAM.

Exactly.

More than the main memory 64KB can only be accessed by soldering inside the CPC. Most users won't like to do this.

[McArti0]

But 128KB video ram without soldering because PAL is in the socket.

[zhulien]

What are you hoping to accomplish? As you say yourself, you can page all of the CRTC accessible RAM out by using the #C2 paging configuration. Other than that, there isn't really a benefit to paging as such.

You can't get a better screen resolution or more colours or anything like that simply because there is 64K of memory present, the hardware just doesn't work like that.

Some demo effects split modes but not only modes, also split the screen with different memory offsets at different screen locations.  I was thinking if we had banked video ram also, it might have some benefits other than a dedicated gfx card.  To me with 128k machines, it is odd not many people put all the code in c2 and use c0 for 32k video ram.

[zhulien]

You can't get a better screen resolution or more colours or anything like that simply because there is 64K of memory present, the hardware just doesn't work like that.

Play Pinball Dreem..
Scroll in 64kb space video ram.
Two pages overscan. ~60 flikering colors.

My 1024x480 resolution. On LCD

Actually that is sort of what I was thinking but with double buffering 32k... or 3x buffering 16k... 

With regard to interrupts, they go to c2 when c2 is banked in, so its not an issue.  The only thing we seem to lose is firmware use... maybe creating a game firmware could be an alternative. 

[McArti0]

Adapter circuit 128kB VRam emulator.

LD BC,&7FCX
DI
OUT (C),C
OUT (C),C
EI

Fast 2xOut toggle Vram to Bank4-7 or back to Bank 0-3.

Change CAS0 and CAS1 signal for non CPU signal

This enables C4-C7 with VRAM at &4000-7FFF. 4x16kB for screen and &C000-FFFF for code.

What do You think?

Schematic PAL in 6128

https://www.cpcwiki.eu/imgs/4/4a/CPC6128_Schematic.png

[andycadley]

What are you hoping to accomplish? As you say yourself, you can page all of the CRTC accessible RAM out by using the #C2 paging configuration. Other than that, there isn't really a benefit to paging as such.

You can't get a better screen resolution or more colours or anything like that simply because there is 64K of memory present, the hardware just doesn't work like that.

Some demo effects split modes but not only modes, also split the screen with different memory offsets at different screen locations.  I was thinking if we had banked video ram also, it might have some benefits other than a dedicated gfx card.  To me with 128k machines, it is odd not many people put all the code in c2 and use c0 for 32k video ram.

16K of video RAM is already a lot for the CPU to deal with and that's without hampering it by using overscan. Yeah, there are demo effects for which it is useful, but they're usually based on repeating parts of the display memory specifically to avoid having to update memory. That's fine for a pattern moving around on screen, but not actually very practical.

32K will get you an overscan screen and, while you could theoretically double buffer it, you aren't going to be updating it all fast enough for that to really be a worthwhile exercise. You could triple buffer a standard 16K screen, but again it's mostly a case of diminishing returns given how long drawing takes anyway.

[McArti0]

Dynamic TEST - 128kB VRAM circuit Adapter

Test Hi density OUT &7F ... , and Low density OUT &7F ...

[zhulien]

Adapter circuit 128kB VRam emulator.

LD BC,&7FCX
DI
OUT (C),C
OUT (C),C
EI

Fast 2xOut toggle Vram to Bank4-7 or back to Bank 0-3.

Change CAS0 and CAS1 signal for non CPU signal

This enables C4-C7 with VRAM at &4000-7FFF. 4x16kB for screen and &C000-FFFF for code.

What do You think?

Schematic PAL in 6128

https://www.cpcwiki.eu/imgs/4/4a/CPC6128_Schematic.png

That's an interesting alternative...

I guess... what is the cost benefit of a banked video RAM solution using the least components possible - since the CPC community it appears doesn't like investing in their hobby.

[eto]

Nice idea. It would be 6128 only I guess. That doesn't seem to be feasible for the 464,664 or the Plus as they are lacking the PAL

[GUNHED]

But 128KB video ram without soldering because PAL is in the socket.

No, the CRTC accesses 64 KB. The PAL got nothing to do with it. Except you change the inside of the CPC.

[McArti0]

You're BIG wrong.
Do you know which pin is not common to all RAM chips in 6128?

[HAL6128]

Dynamic TEST - 128kB VRAM circuit Adapter

Test Hi density OUT &7F ... , and Low density OUT &7F ...

Looked like a very small board extension? You mentioned that some kind of adapter could be placed under the PAL/GAL 40030 (which is backpacked then?)

[McArti0]

You dont know the Power of the dark side 

[GUNHED]

The light is always stronger. Darkness is just an illusion induced by crippled creatures.

[McArti0]

Dark side ... FPGA.

Hm... I don't think PAL is needed at all. Let'go design FULL PAL-MOD.

[McArti0]

GUNHED you didn't answer the question...

Do you know which pin is not common to all RAM chips in 6128?

[eto]

Hm... I don't think PAL is needed at all. Let'go design FULL PAL-MOD.

I already made a PCB that can be inserted into the PAL socket and have some different logic for the internal 512KB expansion mod. While developing it, Toto suggested to incorporate some logic to make more RAM available to the GateArray if I do a PAL mod anyway. I finally did not consider this as it would have required more logic (= more ICs) and it would be inherently incompatible with anything but the 6128.

The latter is my biggest concern. Even if someone would be willing to add the logic, it would not work on anything else but an unexpanded 6128. As soon as you have a different machine or a RAM expansion you end up with the original logic where the GateArray cannot access anything but the primary 64KB.

No, the CRTC accesses 64 KB. The PAL got nothing to do with it. Except you change the inside of the CPC.

In the 6128 all RAM ICs are fully parallel. The PAL drives A15, A14 and both CAS lines. So when you replace/enhance the PAL you can also make the secondary RAM bank available to the GateArray by activating CAS1 while the Gate Array reads RAM.