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RAMDIS question

Started by martin464, 22:12, 27 February 24

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martin464

Say a CPC is running in C7 mode with code in bank 1 @ &4000
If a device were to assert RAMDIS would it be disconnected from all internal RAM except bank 1?
I suppose the question is what does RAMDIS do if not in C2

i was wondering if this could be useful to make a RAM expansion that activates off an IO port
like, any reads/writes outside 40-7F would then be from the extra ram, and there'd be no conflict with the now disabled internal ram

it would be a bit like paging in 48k banks in one go
i sort of hope it wouldn't work because the way it would interact logically with a standard ram expansion could be a bit of a mind bender, there'd be new 'modes' to play with...
CPC 464 - 212387 K31-4Z

"One essential object is to choose that arrangement which shall tend to reduce to a minimum the time necessary for completing the calculation." Ada Lovelace

PulkoMandy

RAMDIS disables all internal RAM of the CPC, it does not matter if it's banks or main memory.

However, that does not work for external memory expansions (X-Mem, Gemini, ...). They use RAMDIS as an output and can't easily also use it as an input at the same time (it would require a different way to wire multiple expansions together, to daisy-chain RAMDIS inputs and outputs of cards into each other).

The external RAM expansion is responsible for setting RAMDIS on each memory access to say "I'm handling this one" and disable access to the CPC internal memory (including internal banks). From there you can implement any mapping you want, there is no need to follow the established standard if you need something more flexible (except of course, existing software won't be able to use it).

eto

Quote from: PulkoMandy on 22:38, 27 February 24RAMDIS disables all internal RAM of the CPC, it does not matter if it's banks or main memory.
But on the 464 (and 664?) only for read operations, right? 

martin464

i hope its not only for reads or ... royal screw job

for now i'm just gonna wire up a 64k extra ram hack and see if it works

the idea is from making that rom boot pcb, what i'll try is adding a 64k sram to it. on ROMEN pulls RAMDIS. so there's an 8k rom and 64k ram. to separate them out will put a logic gate inbetween so it starts off enabling the rom then switches to the ram till its turned off and on. ROM just to boot then subsequent ROMEN's are just enabling the extra RAM (obviously i don't care about the onboard OS/Basic any more)

so using standard expansions they will work, you get an extra 48k, using romen no address decoding or anything totally compatible with everything hw wise (not software true). the only problem is excluding the &4000-7FFF 16k for paging in expanded ram. dont want a conflict. i don't know how to do that but i don't even care for now. instead of 64k a 16k one at C000 will work. 16 extra k is still useful

so i can do on ROMEN
B0 - no data
B1 - page from expanded ram as usual
B2 - no data
B3 - extra 16k

the no data could be usable ram with way to put a gap in there to ignore B1
its all completely free and it could be used as a DMA transfer cache. so your DMA device can safely dump or read off this ram till its needed leaving interrupts enabled and so on
CPC 464 - 212387 K31-4Z

"One essential object is to choose that arrangement which shall tend to reduce to a minimum the time necessary for completing the calculation." Ada Lovelace

PulkoMandy

Quote from: eto on 09:27, 28 February 24
Quote from: PulkoMandy on 22:38, 27 February 24RAMDIS disables all internal RAM of the CPC, it does not matter if it's banks or main memory.
But on the 464 (and 664?) only for read operations, right?

Yes, I forgot to mention that. On the 464 this was added to allow external ROM expansions. They didn't plan yet for external RAM expansions. So, only reads are blocked.

RAM expansions for the 464 manage to do this in other ways, for example by forcing the Z80 /WR line high to prevent writes to main RAM, if I remember correctly. (I have not tried to design such a thing myself).

Quote from: martin464 on 09:32, 28 February 24the only problem is excluding the &4000-7FFF 16k for paging in expanded ram. dont want a conflict. i don't know how to do that but i don't even care for now. 
There is no way to detect what the CPC6128 is doing with its internal banks. The only way would be to have your own implementation of the gate array/PAL MMR register to decide if the expansion RAM is paged in or not.

martin464

#5
thanks Pulko

QuoteYes, I forgot to mention that. On the 464 this was added to allow external ROM expansions. They didn't plan yet for external RAM expansions. So, only reads are blocked.

RAM expansions for the 464 manage to do this in other ways, for example by forcing the Z80 /WR line high to prevent writes to main RAM, if I remember correctly. (I have not tried to design such a thing myself).

yes you are right. so the dirty DK tronics hack would be needed which adds a bit more complexity and fear, now there's 2 devices trying to reverse the signal, is that a risk although in theory only 1 at a time would do it. the fact its a hack doesn't worry me cause it works

QuoteThere is no way to detect what the CPC6128 is doing with its internal banks. The only way would be to have your own implementation of the gate array/PAL MMR register to decide if the expansion RAM is paged in or not.

If we can disable internal ram with RAMDIS+the WR hack then it would be ok. no need to know, it relies on code setting it up first
this is meant for having an existing RAM pack installed so can set to C1 mode
when read/write < &C0 internal ram is disabled, when > &C0 the RAM pack is doing it for us, as we preset that C1 config first in code
it would work better in C1 then the 1st 48k is free in one block

So the code would be something like
* Set C1 mode
* Set CRTC register to enable ROMS (which is just a cheap way to trigger it if one doesn't care about the OS or any ROMS for their project it becomes a spare pin on the expansion bus. An IO method might be less hacky. i know not everyone is as fond of dirty hacks and kludges as me :0 )

then you'd be in the new ram mode with 3 blocks of extra RAM and one of expanded
yes, I did have the idea it could be useful as a DMA cache although totally useless for doing anything cool with screen RAM. just for loading/saving data async into this spare ram area

in effect it's like EXX on the Z80. Swapping out the internal RAM for another set when in C1 mode so the existing banking schema would still work over the top of this. I figured if the circuitry was simple it might make it worth or just as an experiment
but it seems to me this idea to expand the banking options is compatible with the native schema so it is a bit unused/unexplored way to get free ram?

CPC 464 - 212387 K31-4Z

"One essential object is to choose that arrangement which shall tend to reduce to a minimum the time necessary for completing the calculation." Ada Lovelace

andycadley

If you're running code from #C000 and enable ROMs, won't you page out your running code for the ROM? And if your running code is below #C000, then the paged in RAM will page it out instead.

And, if my understanding is correct, it won't work properly on any machine which has external RAM (so no good on a 664 or expanded 6128).

I'm struggling to see a good use case for it, to be honest. We can already have ridiculous amounts of RAM attached and no software that really takes advantage of it. Is there a good case for adding another, incompatible, expansion scheme?

martin464

Hi Andy, this started off as a ROM board project to replace the OS ROM with with a custom. Then I wondered what else I could add to the board

So ROMDIS is already being asserted all the time. The 2nd RAM chip is an add-on to this arrangement with logic to enable the ROM or RAM based on an address line and the C1 paging would occur in the bank 3 @ C000

To clarify the ROM chip only needs a few address lines wired up for about 1k boot code after that its never needed. I was going to use an old 8kbyte chip I have and a 64k static ram so didn't need to worry about memory refresh.

So when it boots it runs addr 0 and loader goes into the C1 bank then it disables the ROMS and we're back to normal

So external RAM is a pre-requisite to this idea. If the internal RAM is disabled and no expanded RAM was able to be paged in, then you'd be stuck with no way to transfer anything


The use case is the 2nd question after figuring out if it could actually work!

I wouldn't say it was incompatible with any of the standard expansions it just adds another mode K1 (for kludge). All existing expansions would carry on working. Yes the ROM method instead of address decoding to control it is just a fudge for my ROM board project. But a better method should be compatible with existing expansions and software. They just won't see it
-Address-     0      1      2      3      4      5      6      7     K1
 0000-3FFF   RAM_0  RAM_0  RAM_4  RAM_0  RAM_0  RAM_0  RAM_0  RAM_0  RAM_K0
 4000-7FFF   RAM_1  RAM_1  RAM_5  RAM_3  RAM_4  RAM_5  RAM_6  RAM_7  RAM_K1
 8000-BFFF   RAM_2  RAM_2  RAM_6  RAM_2  RAM_2  RAM_2  RAM_2  RAM_2  RAM_K2
 C000-FFFF   RAM_3  RAM_7  RAM_7  RAM_7  RAM_3  RAM_3  RAM_3  RAM_3  RAM_7


I will admit the only use case I can see for it, is for DMA caching. Because in that scenario you want a completely separate set of RAM that's accessed as fast as the device can go and leave interrupts running while it does its thing. I don't know if this is actually better than other methods to expose a DMA cache to the CPC or not. There must be other ways to do this with external RAM and a DMA controller, how to expose the DMA cache RAM to the system seamlessly?
I'm a bit obsessed with DMA storage at the moment
 
But I can't actually think of any other use for it that wouldn't be covered just by plonking a bigger RAM pack on you're right about that
CPC 464 - 212387 K31-4Z

"One essential object is to choose that arrangement which shall tend to reduce to a minimum the time necessary for completing the calculation." Ada Lovelace

McArti0

K1 and you have no access to the screen memory. Is this what it was supposed to look like?
CPC 6128, Whole 6128 and Only 6128, with .....
NewPAL v3 for use all 128kB RAM by CRTC as VRAM
TYPICAL :) TV Funai 22FL532/10 with VGA-RGB-in.

martin464

yup, in this config all internal ram's disabled and the top bank is an expansion bank paged in
someone's already got dma working that halts the cpu and i think has 1 or 2microsecond per byte speed limit. this thing here probably will be slower than that cause the z80 must then copy it to the screen ram at what, 4 or 5us per byte even if the initial load is ultra fast. it might suck i don't know yes no waiting for the device and interrupts enabled is a plus, then a minus for the z80 copy, not sure if its going to be faster or not. 

i dunno, i got a feeling there's some use for it... i suppose to be honest a dma device would really need to be a ram expansion as well with some management of it and go direct to its expanded ram knowing what it can hide or expose to the bus when loading/saving at max speed. then the z80 doesn't have to copy anything. but this wouldn't work for the screen ram there's no way to blit stuff direct to it via dma without that limit of the already done solution (which is awesome btw).. but anything to do with data loading/save would go my guess is about ten times quicker maybe way more. but this has nothing to do with what i was thinking about here which is really not ideal. still - good to think about stuff and how different ram banking configs could exist. you know, the stuff you think about driving to work or whatnot

CPC 464 - 212387 K31-4Z

"One essential object is to choose that arrangement which shall tend to reduce to a minimum the time necessary for completing the calculation." Ada Lovelace

rpalmer

Quote from: martin464 on 11:13, 28 February 24* Set CRTC register to enable ROMS
CRTC does not control the ROMs, only the VGA chip can do that. The CRTC can only control the address lines for Video or not.

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