I have a dream ... 8)
The Second Level of TRUBO is within the reach of Mr. Bread80.
In his GA RP2350 you can press the 8MHz CPU mode.
In this thread I wanted to address the possibility of the First Level of CPC TURBO, i.e. faster execution of some z80 instructions via CMOS with a higher clock.
All we need is to change the shape of the WAIT signal for a faster processor or locally change the clock (small speedstep)
How to do it? ... ;D
Linkt to emulation TURBO CPC First Level. (https://www.falstad.com/circuit/circuitjs.html?ctz=CQAgjOB0CcCsDMYBMsCmBaaIAMkAsy88sS00A7EgGzQAcSY8Is2zIeTa6YYAUAErhkQpCJC1WrUWCrY58tq3S5ytBHRlEKePLSa5YAkNCoh42PGdHnLU9vIWwczg0Z7Sd41jMkhpDuT9IJyRgnEh4PGhsKlg1bHg6WlisXCRaXgAPEHQ9cARmUzBYU0skS34AUQBBABEATXQAYQAFJt5ipxM-SnByUyRepGxYW14Ad2NTIiLoawscCeZPME9YOfBPbA6SP3LwdPYqS2RaZ1FWQ0n3MSR9m+3r4VWy+62d1jxjzctRk62-M4ruANjY9pYwY8-HhWMRrPBpsNFp1oVJaGd4Ej0mdhqNmEs7hCFoSrJICftMVIYaTFpMZjSETj0bSzFQcSVwX4OVCSSgBhSFttitY2T1RF8yr07E5gRLwLIjpKLllmHjGKxyOZwER2NCQE0ADIAeSaAGkADoAZwAZgBDS0AFytAC0JLwAJKcl5ejaSMLAknevnysmTYM+LmzZVh6nlVjdOMsxPJ2PMoUFRNgDYp3wXfGTBO9BPU7YAe0BEE+YGwoicuAcFFiVBQzggVTq9V45YglfY1dr4Qb-RKLe8+oNFsteAAsgAJABeXdbzgICUUkCHTdH4Hlc8X5aKK+rnEH8kbI7rO8NJsnru2QA)
It work (or not work) ;D
Project v0.00⅜
Would be nice to see that running.
However, please do consider that a CMOS Z80 has different opcodes (f.e. OUT (C),0 vs OUT (C),&FF ). So not all software will work.
Quote from: GUNHED on 00:02, 17 September 24please do consider that a CMOS Z80 has different opcodes (f.e. OUT (C),0 vs OUT (C),&FF ).
This problem is now a thing of the past.
https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/zilog-z84c0020peg-in-my-cpc-not-all-works/msg239050/#msg239050
https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/zilog-z84c0020peg-in-my-cpc-not-all-works/msg239772/#msg239772
Nothing will stop us! :D
You got an great kind of attitude! Go on!! Software will support your new hardware!!! :) :) :)
i wonder if something like this could work.
imagine a very fast z80 with fast cpc ram. in normal mode they are not enabled like upon boot. they could be enabled either like 6128 plus features or via a port.
when enabled, the fast ram takes place of the standard cpc ram, and the fast cpu is 'available'. the fasts cpu is not automatic, but... maybe it can either be running in slow crippled mode, but software switchable to fast mode, then back to slow mode.The reason for this is... an application when wanting to perform any type of timing sensitive I/O or floppy access would switch to slow mode, but then when wanting to do something fast, would switch to fast mode.
we already have hardware that can use an external CPU instead of internal, and we already have hardware that can use external RAM instead of internal - so likely it could bepossible to do something like this.
timing with the crtc wouldn't be affected i suspect as it will always be looking at the original slow cpc ram.
I don't think the RAM speed would have to matter. You could have "fast RAM" all the time and there would be no change to the system unless you actually sped the CPU (or gate array) up.
Whether you could do that without redesigning most of the motherboard and essentially building a new machine is a whole other matter.
my understanding is the CRTC can only see the internal RAM without modifying the CPC - but as mentioned we already have cards that can have external CPU (you can buy unpopulated ones on ebay) and also external RAM (UliFAC), maybe they can work together
If I am not mistaken, it should be possible to effectively replace the internal RAM with fast SRAM by sandwiching an expansion board between the system board and the socketed Z80, GA and PAL.
With the RAS and CAS lines interrupted, the DRAM on the system board would effectively be disabled.
Since 55ns SRAM can happily run at 16MHz, appropriate glue logic for access interleaving could then enable zero wait state RAM access even with an 8MHz Z80.
Well, at least in my head. I have no idea whether it would actually work.
Switching between 4/16MHz will be via command ED 00/ ED 01 which are free in Z80.
All write/read cycles to internal ram will be the same with Z80 4MHz (Until
@Bread80 decides ;) to make an 8MHz GA version)
All external RAM can work as FAST with 94ns access time for opcodes.
It is enough to mask the low READY signal for fast z80 while accessing external RAM/ROM.
Quote from: Benedikt on 05:59, 18 September 24Well, at least in my head. I have no idea whether it would actually work.
It will work but you have to disable CRTC and include it in the extension.
Quote from: McArti0 on 06:50, 18 September 24Quote from: Benedikt on 05:59, 18 September 24Well, at least in my head. I have no idea whether it would actually work.
It will work but you have to disable CRTC and include it in the extension.
Why disable crtc? Why not shadow it as alifac does?
Quote from: zhulien on 06:20, 19 September 24Quote from: McArti0 on 06:50, 18 September 24Quote from: Benedikt on 05:59, 18 September 24Well, at least in my head. I have no idea whether it would actually work.
It will work but you have to disable CRTC and include it in the extension.
Why disable crtc? Why not shadow it as alifac does?
I don't quite get why the CRTC would have to be disabled or bypassed, at all.
With appropriate address and data latches and careful timing, the CRTC and Gate Array could freely access the 16MHz SRAM in every other 16MHz cycle.
The Gate Array would not have to wait for the value from RAM any longer than with the CPC's slow native RAM.
The 8MHz Z80 would then get exclusive (buffered) access during the other half of the 16MHz cycles. Wait states would only be necessary for I/O.
Quote from: Benedikt on 18:44, 19 September 24I don't quite get why the CRTC would have to be disabled or bypassed, at all.
It's simple. There are no wires with addresses generated by CRTC in the Z80, PAL and GA sockets.
Quote from: McArti0 on 19:04, 19 September 24Quote from: Benedikt on 18:44, 19 September 24I don't quite get why the CRTC would have to be disabled or bypassed, at all.
It's simple. There are no wires with addresses generated by CRTC in the Z80, PAL and GA sockets.
Got it. Well, in that case we need a whole lot of pogo pins. ;D
The basic approach – without pogo pins – would still be interesting for an internal RAM expansion, though.
Quote from: zhulien on 06:20, 19 September 24Why disable crtc? Why not shadow it as alifac does?
CRTC can be read and depending on the version you can receive different values. collisions with other CRTC should not be allowed. Although in fact the second CRTC can be connected as write only.
Some thoughts I've had regarding an upgraded CPC design:
Replace the sequencing logic from the gate array. Then the GA only generates video output and is decoupled from the timings of the rest of the system. You'll need to 'listen' to a GA output signal (eg. CPU or CCLK) to get everything in sync but if they're both driven from the same 16MHz crystal everything will stay in sync once started.
Put a latch between the video bus and the GA. The new sequencer logic can load data into it at it's leisure. The GA can strobe it in via CAS or 244EN. This further decouples the GA from the sequencer and memory and permits the use of faster memory (eg SRAM). You just need to be aware of the GAs version of CCLK when reading video bytes so you get the correct ones. (Probably best to to have a pair of latches for the two video bytes in each cycle).
I/O accesses should probably have wait states generated so old school I/O devices can keep up. If you're doing a full new PCB layout generating a 4MHz PHI for the expansion port will help disk drives etc to run at the correct speed.
Reads from ROM and I/O (except I/O to the GA) don't clash with video reads so the CPU doesn't need to slow down when reading from them. The same for expanded memory. And, if you really want maximum performance, don't generate wait states (or read video bytes) during refresh periods.
The latter item will probably work best if you bring the memory manager into the new sequencer logic (ie replacing the HAL). The HAL is probably not terribly fast anyway (given it's age) so a replacement should enable faster memory accesses.
If you're replacing the HAL you might as well upgrade the memory addressing schema. My preference is that of the Enterprise. This has four 8-bit latches, one per 16k memory bank, and enables any physical memory bank to be patched into any Z80 bank. As with enhanced GA performance the system would need to boot into 'standard' memory manager mode and the enhanced mode would be enabled via an I/O port.
BTW I much prefer an I/O port to a 'secret' Z80 opcode. However adding extra registers to the GA ports is messy. I suspect that shadowing unused CRTC registers would be much more practical, but depends on how the CRTC handles the selection of 'illegal' registers? Does if allow such selections and ignore writes to them, or does it map them onto some default/partially decoded register?
Quote from: Bread80 on 17:18, 27 September 24BTW I much prefer an I/O port to a 'secret' Z80 opcode. However adding extra registers to the GA ports is messy. I suspect that shadowing unused CRTC registers would be much more practical, but depends on how the CRTC handles the selection of 'illegal' registers? Does if allow such selections and ignore writes to them, or does it map them onto some default/partially decoded register?
And I prefer Opcodes because they are faster, because they don't need addressing, and no one has ever used them. CMOS Z80 interface will need hardware patch OUT (c),255 to 0 anyway.
I wouldn't want to kill CRTC 5 (HD6345) in the socket and it has 40 registers.
I checked that in CRTC 0. R0, R32, R64 and R128 are the same register.
At PAL/HAL my mouth is watering at the sight of OUT &3CFF,nn , which nicely bypasses CRTC and GA.
Quote from: Bread80 on 17:18, 27 September 24(or read video bytes) during refresh periods.
I see DMA here with an automatic refresh register counter. I like it very much.
For test I will try CPC Turbo Half Level ;D
Very complicated circuit :laugh:
Link to CPC Turbo Half Level (https://www.falstad.com/circuit/circuitjs.html?ctz=CQAgjOCmC0CcIAYB0sAsAOA7JgzAVnRwDZ908AmIkPBakVHamMMAKACVwxyueWf0tWnyIIx4urWjJMZHLHRgS8zKgyNkeDr3BqQg8KMQg+4ieSR4TlxEhypYCIgRrz06Z-GTl0rAB4g0ITgeIx4VGDh9CaoIOwAogCCACIAmtAAwgAKGawA7vREsdzo1NzgPoj5Ovwm5MXlCNW1YHrk9bqxTQGoqlyxzrQsmNEdGQAyAPIZANIAOgDOAGYAhgsALosAWoL+hSP1A2Dw9SOxHQDqiQCSACqLqxvbuwVEHeRRqEomUd2GtPBwqVyudYtkMotbgBVdgAIUmiwAEolxgAxRbjeIANXi40WAC5oMlFot1gB7UmQDasa4gYilD5UL5URnGTTUGl08jCKL0n5UIQ2LS08iYHisnDc-lsoWc9rnKKi8W-WxWLQFeXSzWtLqsAAmdQayoi5R4esgqwArgAbdb6w2daU6kwgc1W23VVnOr2VJoaqIlJ2NOUByo4YgVUqCtWc8MRSqoIqRmUxzhKYTuECwFmZ4T0MxiSQp1hk8Au2hfBA8KzIMywTDON41ssJFKpEvGHgVsAIRgWGtIOsN8IfYwQJQAWURAC8O33jJWwrYh43R0MQBNpvMFjsmqWGQue0va+J66vmxArncO+QIF36EfrAOVyOL-Qp7OgA)
Quote from: McArti0 on 17:54, 27 September 24I wouldn't want to kill CRTC 5 (HD6345) in the socket and it has 40 registers.
I checked that in CRTC 0. R0, R32, R64 and R128 are the same register.
I didn't realise there was a version with extra registers. That's a shame. I'd really like to be able to add extra GA registers. The current scheme is a little ... cramped.
Is the hd6345 used in the CPC?
Quote from: eto on 16:54, 28 September 24Is the hd6345 used in the CPC?
No, not in any shipped model.
Quote from: eto on 16:54, 28 September 24Is the hd6345 used in the CPC?
"Yes" :D
https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/would-you-like-to-have-crtc-5-in-your-cpc-about-hd6345/msg240088/#msg240088
Houston we have the three problem.
8255,CRTC, and ... Z80C
:laugh:
One clock Z80 16MHz have 62,5ns
https://www.zilog.com/docs/z80/ps0178.pdf page 20... (24 original)
MREQ is delayed so much that it comes within zero distance of the decision to trigger WAIT.
For GA time T1 to RAS, T1 cant to be fast 62,5ns clock with 57ns delay to stable ADR.
The Z80C has a highly non-scalable timing plan. The datasheet says it depends on the capacitance on the pins.
CRTC needs a stable ADR 140 nseconds before IORQ. The Z80@16 won't do this.
CRTC needs 450ns IORQ. IORQ for CPC will have to be artificially delayed.
For slow 8255AS-5 IORQ must be slower (needs 250ns) than Z80@16.
Link to emulation TurboCPC HL v2 (https://www.falstad.com/circuit/circuitjs.html?ctz=CQAgjOCmC0CcIAYB0sAsAOA7JgzAVnRwDZ908AmIkPBakVHamMMAKACUQdiR1buqGRCHLgiCCZLq1oyTGRyx0YEosyoMjZHg7gwosBt60VtWgclTySPCJuIkOVLARECNRenRv4yculYADxBoQnA8RjwqMCj6EVQQdgBRAEEAEQBNaABhAAVs1gB3aiMWUTdo-UQivQNS-3AjBCCQIjBMEFhbTFhGJTjyBOyAGQB5bIBpAB0AZwAzAEMZgBdZgC0+FraE8lcQTCIqXfgdhIB1FIBJABVZxZX1zeKKkUH6IXI35uDTTupvcCiU4gPLZWbXACq7AAQqNZgAJFLDABis2GSQAaklhrMAFzQNKzWYAYwA9gA7YmQAAOyy2hi4RHgB3QXEwQPiIEuo3YAEU7ktVjMNs1ioRRDh0AlxKzJQlmpcRAhZRRGgl8KIzPYdMVdirRHquFLqrrlUaEkI5dVFbAqBr6PrhNpqKwYkDZURWdAcBLPcJNS6flUcAgJQh1QhbDtaGlsSkMrNuXzZgA-QwIckzXRefjh3i2ri7f3gSwSOy2ay2HBIQwxWCUCIEWA9LRIKU1b2+r0+kRearBOAdcjs6hHTBRzlJ-nzUkAJ1moN0AnA9a4PHIsXM9FLtFsZgcOsBrMMCX0rM+8pqZ9eFo+XxqMvNStlxtFYhMBxEsXaVDfvx-75qiagEnkeQFvsuZRrtE4jVG60HgJ+DAGJ+W62IeyFgZhAHNDEjAbjB-A8L8W67qwir-kYhqgVq6GsLOz5AQR4G8DQEisMSX7RFR35VAYzAQMgYDKLsCDslE6DkCwZC-kgEhsAA5lxtTKQWZisAAJspvzUbBogaZAiwAK4ADZ0qax56WaNE1MxOnfk0ro0PQPZQXgpRVGhLoxBAy4FphakiHQOjBP00kiNwgIQNGIAAMqQEKKgALKzNSkCzgAlqSGlORAOaFrQ4oFcWdE+bwfBPkVVqkS6Yo9j6hUVcQrJvlVxr5cuuF4LY9ayjwzZ2sRoaXrsHQvFBnrHlUQzDBMrCjSWsTNSWfbLTNc0LS8F6tH223nFc1zzWJJZvJBkaDYIIAXDcNT5agZa9du6kUedjLHsNb1OtqrAAEbGPuLBgLQqB4IJNQFvaEM8M0WkQ6qoH2vphkLKZdJKQW-ishjI7qZxUNUBju1QNALD0CgNB8HwoNEOyODqA48n0Z0F1AZ14SSFeRj2gj0MtDJiHwF0p6SQMCQbKg2Shs0pLgEFwNA6Ie5yZIA1RBuwgQMk6QZKwMs1agQP4fYyCWKrRDqyYYhJfCABeutcHL9CG9IysSGbFuyyM4zTMKmwy0OwgGwgkQMyrBxq3usvXYdMtFgGQdG0rpvh+bkfRbM1t27HAfy8HLvJxUHsQMlqXpVlOUy0DjtB4roduynRdcjyvL28J1cKy7glBW3jBTncc4LvkrBAA)
Antidote to problems....
That's ridiculously slow logic!
The Motorola datasheet on BitSavers has nicer timings, especially for later revisions https://bitsavers.trailing-edge.com/components/motorola/_dataSheets/6845.pdf
Using an RC network for such delays leaves me feeling queasy. I'd prefer to see a couple(?) of latches trigger by a clock edge. Eg with a 74xx74:
Clock to CLK (inverted if need to be to the correct edge)
/IORQ to D
inverted /IORQ to the /SET input
I'm not sure how you're generating /WAIT but I'd use a similar strategy there (to lengthen the /IORQ pulse as needed).
And I'd probably to that for all I/O to OG devices as they'll all be pretty slow compared to a 20MHz CPU.
Quote from: Bread80 on 12:16, 12 October 24Using an RC network for such delays leaves me feeling queasy.
This is just delay marking for simulation purposes. :laugh:
Basing a precision delay on 10pF would be fun ;D This is basically the capacitance of a protection diode on the TTL input.
In the link to the emulation I wrote that it is a concept.
The circuit is based on the counters in the SLG46826v-DIP.
Yesterday ROM and CRTC worked but RAM or NewPAL and GA were not set.
I thought I would be able to run it without using an oscilloscope like in the 90s, but I found that I was already being doped by the figs on your website.
I bought two cheap zt-703s and dpox180h. I'll check if they are suitable for such applications.
Quote from: Bread80 on 12:16, 12 October 24I'm not sure how you're generating /WAIT but I'd use a similar strategy there (to lengthen the /IORQ pulse as needed).
In this version WAIT is original from GA. IORQ I have 20ns extended by propagation on gates, but shortened by high clock tick no. 3 and 4.
Quote from: Bread80 on 16:30, 28 September 24I'd really like to be able to add extra GA registers. The current scheme is a little ... cramped.
Out &7fff,'B' and &3F
Out &7fff,'r' and &3F
Out &7fff,'e' and &3F
Out &7fff,'a' and &3F
Out &7fff,'d' and &3F
Out &7fff,'8' and &3F
Out &7fff,'0' and &3F
Out &7fff, R0-63
Out &7fff, nn
A=Inp(&7fff)
First version Turbo CPC Half Level is working. ;D
Benchmark v1.0 - 575 to 515 (+11%)
Benchmark v1.0 559/515=8,5%
BUT IORQ is unchanged.
FDD 765 works perfectly.
SymbOS 4.0b works perfectly.
@Prodatron write benchmark. ;D
Benchmark v1.0 574/515=11,4%
Benchmark v1.1 67/58=15,5%
1 DEFINT L:AFTER 50 GOSUB 5
2 L=L+1:x=SIN(45):GOTO 2
5 PRINT L
ps. CP/M Plus works well.
Quote from: McArti0 on 20:10, 18 October 24Benchmark v1.0 559/515=8,5%
BUT IORQ is unchanged.
FDD 765 works perfectly.
SymbOS 4.0b works perfectly.
@Prodatron write benchmark. ;D
Is that really true? So you are going to make it? That sounds fantastic!
Quote from: Prodatron on 20:43, 18 October 24So you are going to make it?
I have it ... :laugh:
The 4MHz PHI is used to generate the clock signal for the data separator in the disc interface (DDI-1 or on board), so I assume you're still clocking that at 4MHz and just feeding a higher frequency to the Z80?
@Bread
YES! PHI Z80 is one separate Pin only.
Link to emulate Turbo CPC First Level v3 (https://www.falstad.com/circuit/circuitjs.html?ctz=CQAgjOCmC0CcICYB0AGFAOArJgzANlgRzHQHY9SRMUqQAWHKmMMAKACUq8b0bNv66EDQThuaCbRrQUSUlhyx0YPDkWk6ddI1mYOgxBjGIEdYYnATJyTIiS3ZOOrBR5MWFIvTo38WQnRWAA8QaDA6SgQwSmghBAQaM1MQdgBRAEEAEQBNaABhAAU81gB3EG1RBH4QWE1EapRSgwShWDxDIUaQl1sieDAMCFNRJLM8gBkAeTyAaQAdAGcAMwBDBYAXRYAtXmCQNXb4UlIaMBHEMaLFgBUAVXYAIUnFgDEASXYAZWvF8dSANVS40WAC5oJlFosAMYAewAdlDIAAHdb6fg0A5cRJocwjKw4hzmXRNNodGrtXjCJqYAL7FBmPDJHD0qlgGkgRlmHAJECkHncmgiWh6Mp8kR83n8nmNNmMfBCZlmGkKllCvisNk0MX1CncnW44UazAQTkXLU80yCiy2PQhCKRbwcs6IWAQJI0T6QTYLFQAWUWSMgACcAJYwgAmrASlFqSWqsHI+rG4xmGrwZjAhHAtMt2aExp5Zj4wpAqwANgtIDVqQJKTh2ZTGmUBeUMTzSU3ya2893Oy2WvseZnRH2WQOAkJh1SyggJePqlPO1V2uPkoujYwzq0V8kOxZ1WUt+BnUeJ9Oe2fL46l46z-LENemvflfs8ArpU0jy+zy-O0f66IX60jKuA9pi8RcvgBoHkmWgmGYDAjk0s4jHBy70Hqo4IWhjqIeeLaaO+iSYU+UpthiUF9uyLY0R+KgZlm965s+ZyJOYNq0OWlbgHQJIrkYpItp2glDrSQlPtR-INoKpE8Bi0lUiEfT7No+yZip7SjCAAC2EaLOEeymJudAQMy-R1FpunhossCsG8D75mJb5UMBwj2FQRqVLeRhXp09CGmyXlCIRDkuX5SoefZ6LwRyyQQexBJNKa6Gmoq57RZS0XxZ20WYqllGsDC4D7vQAyiA4qASAmbiMoSEBpFk2SFdBpWeFIlVoNV-BVOYEB+gAEgAXs1jAjq1jAVVYXW1b1IATNM8wLDsjRFZE5gmW1k1VeQ3V1fQiy+kNzXwGNG0TW5U07TNpxiP6CyBqGEasEAA)
What should be faster (for add 5 fast clock )...
| OpCode | M cycles |
| PUSH IX | 5 to 4 |
| PUSH ss | 4 to 3 |
| LDI | 5 to 4 |
| LDIR | 7 to 5 back to live!!! |
| CPI | 5 to 3 |
| CPIR | 7 to 4 |
| ADD A,(IX+d) | 6 to 4 (to try 4,4,3,5,3) |
| ADD HL,ss | 3 to 2 |
| ADC HL,ss | 4 to 3 |
| INC ss | 2 to 1 |
| INC IX | 3 to 2 |
| LD SP,HL | 2 to 1 |
| LD I,A | 3 to 2 |
| JR C,e | 4 to 2 |
| DJNZ e | 5 to 2 :-X |
| RST p | 4 to 3 |
| OUTI | 5 to 4 |
| |
correction after https://www.cpcwiki.eu/imgs/b/b4/Z80_CPC_Timings_cheat_sheet.20230709.pdf
| OpCode | M cycles |
| PUSH IX | 5 to 4 |
| PUSH ss | 4 to 3 |
| LDI | 5 to 4 |
| LDIR | 6 to 5 back to live!!! |
| CPI | 5 to 3 |
| CPIR | 6 to 4 |
| ADD A,(IX+d) | 5 to 4 (to try 4,4,3,5,3) |
| ADD HL,ss | 3 to 2 |
| ADC HL,ss | 4 to 3 |
| INC ss | 2 to 1 |
| INC IX | 3 to 2 |
| LD SP,HL | 2 to 1 |
| LD I,A | 3 to 2 |
| JR C,e | 4 to 2 |
| DJNZ e | 4 to 2 |
| RST p | 4 to 3 |
| OUTI | 5 to 4 |
Quote from: McArti0 on 20:10, 18 October 24SymbOS 4.0b works perfectly.
@Prodatron write benchmark. ;D
Did you try the SymbOS performance monitor?
https://www.symbos.org/appinfo.htm?00033
The CPU test contains three parts, simple (=LD A,A ), "complex" (=EX (SP),HL ) and 16bit instructions (=ADD HL,xx).
I wonder if the Performance Monitor already show significant differences between a normal CPC and your CPC Turbo.
Yes, yes, I've already found it. Unfortunately I still have 128kB and 512kB not soldered. Performance Monitor needs 192kB. So now I'm soldering and crying. ??? ;)
Scope DPOX180H come in.
CPC Turbo 3 normal clocks + 5 fast clocks has sometimes problem with seek floppy tracks.
I will try to separate ADD HL,SS and set 2 normal + 9 fast clocks.
Very interesting! Thanks for posting!
As you can see the Turbo has most effects on 16bit additions and similiar commands. Interesting that there is a difference between ADD A,A:... and EX (SP),HL:...
Your setup looks crazy wild! :o :)
Now SymCALC can be faster 16,5% at 3+5 MHz
SINtest.SCS can be run on SymCALC with TICKS function.
https://www.cpcwiki.eu/forum/applications/excel-for-the-cpc-symcalc-spreadsheet-application/msg244596/#msg244596
SymCalc is using a huge mixture of Z80 commands for all this recalculation stuff.
So you have +16% here. Compared to the "complex instructions" (which is just ADD HL,dd ) it is less, so it seems that in the whole process the "simple instructions" are still dominating a lot.
SkyCHART Star 3magnitudo OldCPC Redraw with precision Math 102sek
CPC Turbo 3+5 Mhz -79sek 130%