Hi everyone,
I started my first project and designed a small ROM setup the DiagROM, it allows to put in a single (E)EPROM to put in the DIAG Rom from
@llopis. Thanks for writing it and inspiring me for my first hardware project.
(https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/diagrom-a-small-mx4-board-to-attach-a-diagnostic-rom/?action=dlattach;attach=36501)
So for now the design is ready and is pretty simple. It just requires 8 components (+2 sockets) to make it happen.
It is specifically designed to fit into an M4 board, but you can exchange the MX4 board just with a connector cable.
I thought long about the point of adding the capability to also run upper rom 0. I do have the space, but I did not see any benefit, as this can be run from any normal rom expansion without any issue.
So it is plain simple now and I am now going into testing mode (breadboard first for the logic, and then ordering some PCBs).
Attached you find the PCB shot + a beauty shot of the board. I could have made the dimension even smaller, but then the routing for the EPROM just looked ugly ... It hurts my esthetics..
Congratulations on your first project! You could save a lot of PCB by rotating the ROM 90°. Also, mapping a ROM to the Lower ROM 0 position can be done with even less components. The 74LS02 isn't required: https://www.cpcwiki.eu/index.php/LowerROM
Bryce.
Quote from: Bryce on 09:10, 03 March 22Congratulations on your first project! You could save a lot of PCB by rotating the ROM 90°. Also, mapping a ROM to the Lower ROM 0 position can be done with even less components. The 74LS02 isn't required: https://www.cpcwiki.eu/index.php/LowerROM
Bryce.
Do you sell those boards? Or are files available to order the PCB somewhere?
Quote from: Bryce on 09:10, 03 March 22Congratulations on your first project! Also, mapping a ROM to the Lower ROM 0 position can be done with even less components. The 74LS02 isn't required: https://www.cpcwiki.eu/index.php/LowerROM
Bryce.
Interesting. I thought about the idea of just pulling ROMDIS high and simply disable internal ROMS. But I thought it might be good to have a complete implementation that does not interfere with a Upper ROM 0 you want to have on another upper ROM board (such as M4 or MegaFlash or whatever other solution).
But esp. for a DiagROM that could be even cheaper (and smaller):
QuoteYou could save a lot of PCB by rotating the ROM 90°.
Yeah, I figured that out, even if I was not afraid of PCB space in the first place. However the Mother X4 got me nightmares. The IDC connector is actually not connected correctly - Pin1 of the IDC connector is not Pin1 of the board. The first design I have will not work because of that. So I made a new design with the switched IDC connector, so that Pin50 of IDC is actually PIN1 of the board.
@revaldinho do you have any background why you oriented it this way?
I now created a new connector in KiCad. The famous IDC50 Horizontal CPC connector... Instead of Pin1 on the upper right, it is now on the lower left if you look at the male pins.
Quote from: etoDo you sell those boards? Or are files available to order the PCB somewhere?
I do plan to build some and can also sell one, but it will get eventually fully open source and you can build your own. Currently I am in prototyping stage and the design is not final. So it will take some time still to get it ready.
Quote from: SerErris on 11:54, 03 March 22I do plan to build some and can also sell one, but it will get eventually fully open source and you can build your own. Currently I am in prototyping stage and the design is not final. So it will take some time still to get it ready.
LIKE... but to be honest, I asked
@Bryce if his LowerROM PCB can be bought or if the files are public which can be used to order the PCBs. ;-)
QuoteThe IDC connector is actually not connected correctly - Pin1 of the IDC connector is not Pin1 of the board. The first design I have will not work because of that. So I made a new design with the switched IDC connector, so that Pin50 of IDC is actually PIN1 of the board. @revaldinho do you have any background why you oriented it this way?
I now created a new connector in KiCad. The famous IDC50 Horizontal CPC connector... Instead of Pin1 on the upper right, it is now on the lower left if you look at the male pins.
I'm not sure what you mean here.
All the CPC board's I've seen have the IDC connector on the front, component side. For example, see the M4 Board (https://www.cpcwiki.eu/index.php/M4_Board) or XMEM (https://www.cpcwiki.eu/forum/news-events/x-mem-a-new-memory-expansion-for-all-cpc/). My boards follow the same convention and plug right into an Mother X4 or any other compatible motherboards.
Okay here are the new shots :-) ..
Quote from: revaldinho on 14:18, 03 March 22I'm not sure what you mean here.
All the CPC board's I've seen have the IDC connector on the front, component side. For example, see the M4 Board (https://www.cpcwiki.eu/index.php/M4_Board) or XMEM (https://www.cpcwiki.eu/forum/news-events/x-mem-a-new-memory-expansion-for-all-cpc/). My boards follow the same convention and plug right into an Mother X4 or any other compatible motherboards.
The point is that Pin1 of the IDC connector is not Pin1 of the CPC anymore ..
https://github.com/revaldinho/cpc_ram_expansion/blob/master/cpc_backplane_edge/pcb/cpc_backplane_edge.v explains it as well ... (if you search for it).
Edge connector:
| edge50w CONN5 ( |
| .p1 (Sound), .p2 (VSS), |
| .p3 (A15), .p4 (A14), |
| .p5 (A13), .p6 (A12), |
// Amstrad CPC Edge Connector
//
// V1.01 Corrected upper and lower rows for male header.
Conn0:
| idc_hdr_50w CONN0 ( |
| .p50(Sound), .p49(VSS), |
| .p48(A15), .p47(A14), |
| .p46(A13), .p45(A12), |
The IDC connector itself has a Pin1 and the MX4 board has missaligned it. It is not a problem in itself, but you need to be pretty much aware otherwise it will not work.
attached some explanatory pictures. I have created a Kicad Footprint (cloned it) to reflect that.
OK - this is just the way the footprints for the IDC connectors are described as provided in the various KiCAD and Eagle libraries.
R
Quote from: eto on 14:12, 03 March 22Quote from: SerErris on 11:54, 03 March 22I do plan to build some and can also sell one, but it will get eventually fully open source and you can build your own. Currently I am in prototyping stage and the design is not final. So it will take some time still to get it ready.
LIKE... but to be honest, I asked @Bryce if his LowerROM PCB can be bought or if the files are public which can be used to order the PCBs. ;-)
No Problem with me :-) I am not jealous. I developed it mainly for my education and for having a debug rom. If anyone else want to make one. No problem.
And yes
@Bryce version does the job specifically for the debug rom and is very easy to build. Actually you only need the eeprom, one capacitor and a resistor and thats it.
If you use it just for the diagnostic rom, you could put it directly on a edge connector. and have therefore a very small and pretty cheap module. The pcb would be the most expensive part in it.
Quote from: revaldinho on 15:25, 03 March 22OK - this is just the way the footprints for the IDC connectors are described as provided in the various KiCAD and Eagle libraries.
R
Yes absolutely. Just saying it confused me ... If I would have looked at your verilog file for the X5 motherboard I would have found out early...
The fun part is .. looking at the verilog file, it looks you did the same mistake in V1.00 ;-)
But now I learned how to do routing in multiple orientations .. And I am glad that the header sits in this hardware as it does, otherwise the routing would be even more painful.
The comment is a bit misleading, but I definitely had the inner and outer rows of the connector swapped over on my very first RAM card. The ends of the connector were in the right order though, so I was able to work around the problem by just mounting the connector on the back for that first cut ! :D
The revised connector and comment have been cut and pasted into all the netlists for my other projects ever since, although the comment only really refers to that original RAM card. I should probably tidy that up.
(Being able to cut and paste know good sections of boards in text from one project to another is one of the reasons I stick with the netlister tool. Very convenient.)
I see :-) I have a CPC kicad template I use which has the expansion connector fully netlisted and then I can start from there.
Here is my current schematic of V1.01.
As I said I will provide everything under opensource, but want to validate before with a real PCB.
Cheers
Ser
PCB is on order with JLCPCB. That was the cheapest shipment I could find. The board is so cheap .. 100 of those will cost 18€ to produce. So one will be 18 cent ;-)
Quote from: eto on 10:45, 03 March 22Quote from: Bryce on 09:10, 03 March 22Congratulations on your first project! You could save a lot of PCB by rotating the ROM 90°. Also, mapping a ROM to the Lower ROM 0 position can be done with even less components. The 74LS02 isn't required: https://www.cpcwiki.eu/index.php/LowerROM
Bryce.
Do you sell those boards? Or are files available to order the PCB somewhere?
I made a batch of them a few years back, but I haven't made any since. I don't think I have any left, but I have the layout file somewhere if you want to build one yourself.
Pedantic mode: Lot's of talk here about "IDC" connectors: Neither the MX4 nor SerErris's board contains an IDC connector. I assume you are talking about the 2.54 pinheader. :)
Bryce.
I love it, the first time I found out (wikipedia) what IDC actually stands for and the the connector we are talking about is called "shrouded" pin header "with notch key.
And as stated already, the connector on the X4 is (pedantic) not put in in the right orientation. Pin1 of the connector is not Pin1 of the signal path at all. That does not matter but is confusing.
@Bryce do you have the german name for the connector? I always have issue to find them here at the suppliers, because I only know the english terms.
/edit: found it:
https://de.wikipedia.org/wiki/Stiftleiste
Quote from: SerErris on 17:30, 03 March 22PCB is on order with JLCPCB. That was the cheapest shipment I could find. The board is so cheap .. 100 of those will cost 18€ to produce. So one will be 18 cent ;-)
This is the eternal idealistic vision, in the best of all possible worlds. The reality is that you have done the work for incapable peoples out of passion, but who will sell it very expensive on eBay to the detriment of CPC users. ;-)
If I would want to do a business out of it (which I do not) I actually needed to calculate a lot in there.
My time and effort, shipment cost, component cost, ... something I want to live from ;-).
Luckily I have no time to do a business on that and the business here would be by far to small to actually replace my main job.
And also I question how big the market would be for such a very specialized device that only has two use cases.
1. Run a other OS (need to get complemented by another expansion for other ROMs)
2. Run a diagnostic ROM (how many people actually need that?).
So if I would actually need to make a business out of it, I would stop right here, because I would never get back the development cost.
So I ordered now 10 pcbs. If they are working as expected, I would have 9 for sale. Pricing to be defined. One PCB is around 1€ + components ... so maybe in the 5€ ballpark + shipping.
If you want you post your interest here and I will come back to you if this is working.
Okay here are some news on this project:
1. I validated the design on breadbord ... pretty chaotic to put over all the cables from the bus, but Mother X4 is helpful for that as well :)
2. It is working - So the lower DiagROM is sitting on my breadboard and runs the test ...
3. The DiagROM is actually Lower AND Upper Rom 0 .. AARG ... how could I miss that ...
Now I need get back to the drawing board and consider my options.
The design works if you have another ROM board of any kind and but the upper rom in there.
But if you only want to have one board with both parts, my bord in current layout cannot support it.
So I will get back to the drawing table and check what logic I would need to make lower and upper rom selectable and save to operate with other ROMs in the system (e.g. ROM 1-15). So I would need to put in a ROM selector and that might be overkill. luckily I can do it with a 8in NAND gate and one of the NOR gates, but also I would need to check A13 for and I would need a 1bit latch.
All of that might be overkill for actually beeing able to have a lower rom board that can run the DiagROM.
But challenge accepted, lets see how it turns out.
So the current board (still pcb validation required) will work, as long as you have another ROM option for the upper rom. The good thing is, anything will work as long as you have a Mother X4 board.
Here is the logic for the V2 design:
First part is to latch Rom0 for upper rom selection. This is done via the 8 input NAND which generates high if we have ROM number 0 in D[7:0]. The clock of the latch is generated by checking if both A13 and IORQ are LOW and inverting it (NOR).
The second part then activates OE if either Upper or Lower(0) is selected. Both can be deactivated.
There is one challenge I cannot get my head around. I cannot find a way do save one nor gate or one inverter. both would remove one chip. So the inverter only has 2 of 6 gates used and the nor has 3 of 4 gates used.
Anyone spot a way on how to do that?
Alternative I could go with SMD and use a single inverter and use the NOR gate for the other inverter.
Yes - don't use the 3 input AND, and instead swap it for a 3 input NOR with a little reconfiguration of the inputs.
AND(NOT(ROMEN_B), A14, Q) = NOR(ROMEN_B, NOT(A14), Q_B)
You have Q_B already available, move the inverter from ROMEN_B to A14 and replace the 3 input AND with the 3 i/p NOR.
Now you have two spare 3 i/p NORs in the same IC and can use those for the two inverters.
No more HCT04.
BUT ...
QuoteFirst part is to latch Rom0 for upper rom selection. This is done via the 8 input NAND which generates high if we have ROM number 0 in D[7:0]. The clock of the latch is generated by checking if both A13 and IORQ are LOW and inverting it (NOR).
.. the 8 input NAND will generate a 0 if all inputs are high, and a 1 if any of the inputs are low. You need to make an 8 input NOR to generate a 1 only when all inputs are low.
Can I play ;D
FPGAs and CPLDs are great, but 74 series is much more retro fun! :D
It's the way forwards. Or backwards.
Is it really required to disable the low and high ROM separately?
Quote from: TotO on 15:05, 05 March 22Is it really required to disable the low and high ROM separately?
Yes !
Where is the fun without that option ;D
Quote from: geraldYes !
Where is the fun without that option ;D
Only to use less parts. ;D
Thanks for all your input and good catch on the 8NAND gate.
So today I have a break, tomorrow I will restart refreshed.
Regarding the separated enable. If you just would want to use it purely for diagnostic, you can leave out the complete logic snd just pull ROMDIS high with a resistor use just romen to enable the rom.
So I needed logic to correctly handle the upper rom (not to interfere with other roms) and then the additional jumper is not that big of invest.
Looking at the other thread here about the Diagnostic ROM, I found out, that the Dandanator can activate/deactivate the EPROM lower ROM on demand.
The method it rather clever, but nothing that can be implemented in simple hardware.
The Dandanatro has a CPLD and is sniffing the M1 cycle (instruction fetch) of the CPU. So it reads the memory bus on activation of M1 and MREQ (and maybe even read, i did not dive into the details yet). However if reacts on a series of &FDFDFDxx commands which is an actual Z80 instruction that does nothing to the CPU itself and then doing a simple load afterwords (the load itself does not matter), it is only indication for the CPLD to act. Based on this activity - the CPLD sets up an internal register to reflect the status of the lower rom and either reacts on ROMEN or not. The Register Part and the AND is not a problem. However checking 3x FD in a row and reacting on you need a state machine for it to do it, and setting this up with simple TTL logic will not work in any decent #of chips.
I am not sure if my bord still makes sense? Yes you could run the diagnostics ROM ... but you will not be able to test your internal ROM, because thise functionality that is required to page out the external lower ROM is missing.
The only chance would be to change the ROM and the board to work on a different approach.
As the Diagnostic ROM can only check the first 16 upper roms with its routines, I could use the bit 7 to activate or deactivate the lower EPROM.
0x1000xxxx lower rom 0 disabled
0x0000xxxx lower rom 0 enabled.
That would give me the potential to do a simple thing:
;C holds the ROM selection #(0-15)
;Deactivate Lower ROM
LD B,&DF ;RomSelectAddress
LD A,&80 ;Set bit 7
OR A,C ;of existing C
OUT (C),C ;output C to &DFxx
;C holds rom configuration number
;Activate Lower ROM
LD B,&DF ;RomSelectAddress
LD A,&7F ;deactivate bit 7
AND A,C ;in C
OUT (C),C ;Output C to RomSelect Address
Do you think that is a feasible idea?
Okay, new Version ... now V3.
Schematic attached.
The glue logic now reacts on:
NOT(A13 OR ~IORQ) => ROMSEL (CLK for the FlipFlops)
OR(D3:D0) OR SW1 => ~HISEL0
D7 OR SW0 => ~LOSEL
~ROMEN OR A14 OR ~LOSEL => ~LOOE (low OE)
~ROMEN OR NOT(A14) OR ~HISEL => ~HIOE
~HIOE OR ~LOOE => ~OE
NOT(~OE) => ROMDIS
Features:
- enable both ROMS (Upper0 and Lower) via Software.
- Lower ROM enable/disable mechanism is compatible with normal Firmware behaviour (default is enabled if present).
- can permanently enable Lower Rom0 (switch SW0), this overwrites any software flag.
- can disable Upper ROM0 (SW1).
Considerations:
- You can only select both parts together, the software enable/disable are not independent of each other. You need to multiplex both into a single upper rom select OUT.
- Any normal upper rom enablement will also enable the lower ROM, regardless if it was disabled before or not. I am not sure if that is any problem with the Diagnostic ROM. For any other it is no issue, as you will never disable the lower ROM, but use the normal ROMEN flag from Gatearray (which will just select LOWER or RAM).
- I would love to find another way of disabeling it, so that it could be set independent of the upper rom selection procedure. I need to revisit the Hardware Expansion book on that. I thing there are unused bits ... So I could use one of those perhaps instead of D7.
When the dips are not set to 5v, the 74*32 inputs are floating?
Hmm .. you are right ... I need a pulldown...
Okay, I decided after reading the "Das Schneider CPC Systembuch" to change the selection of Lower rom to the decoding method of the Expansion port BIT together with Bit4. So it would be a A10 OR A4 => ~SELECTLOWER.
That makes a selection of the Lower ROM completely independent of the Upper ROM and the normal Upper ROM logic applies.
So as soon as Lower ROM is disabled the internal CPC ROM will kick in. I am actually thinking of disabling both, but now I need to study the source code of the Diagnostic ROM to understand how it is used to select deselect the individual parts.
It is such an interesting topic :-)
Checking the sourcecode for the ROM the lower rom is only disabled for a single purpose (checking the build in lower ROM). So I wonder if I actually need a separate solution or if that solution I do have in V3 is good enough?
The alternative would require to decode both A10 and A4 and needs more logic.
Decoding A10+IOREQ into CLK + A4 as register value.
It would require two independent D-FlipFlops with independent clocks and also another OR gate ... All that for the purpose that it is most likely only needed for the Diagnostic ROM and I could actually use the other method for that as it is exactly turned off and on a single time (ROM test).
I am not sure if any other configuration ever wants to turn off the lower ROM and instead use the internal one.
A10 is related to the external peripherals like the FDC and the COM expansions.
A10 is related to external peripherals, that is correct but then the lower 8 bits are getting analyzed.
Really the German book "Schneider CPC Systembuch" is great:
https://k1-spdns-de.translate.goog/Vintage/Schneider%20CPC/Das%20Schneider%20CPC%20Systembuch/z89.htm?_x_tr_sl=auto&_x_tr_tl=en&_x_tr_hl=de&_x_tr_pto=wapp#A
So for accessing the Disk controller for instance you have to check A10 AND A7 are low.
If you look at the table in the book bits A2 to A4 are free and not used by the CPC ROMs or hardware in any way. So a possible way would be to check A10 and A4 both are low.
But as I said, this is a very unique requirement. Who normally wants to be able to disable the external lower ROM completely?
I did now however enabled the board to select the Upper Rom as 0 or 1. I had one spare NOR gate I could use to invert D0 and with a switch I can now select either 0 or 1 to be evaluated for the ROM address.I also added the missing pulldowns (Thanks
@TotO)
@TotO)
Okay, now after deep diving the source code of the Diagnostic Rom I figured out, that I do not need the upper ROM at all ... :picard2: and I revalidated this with my breadboard version. Indeed it runs perfect without the upper ROM. Just seeing two ROMs actually made me think that I would need both, but that is actually two different incarnations of the same thing. You can run it as a lower ROM and then do deep dive diagnostics in case Basic does not even start. And you can run as upper ROM with |DIAG command to get it going after Basic has been loaded.
So I am now back to the lower rom and to have a way to switch it on and of via software. This will be simple now and much cheaper ... Ouch. :o
Okay. ... reverting back to version 1 and implementing a way to disable it. Anyhow I learned alot and that was the main goal for this project.
Me beeing stupid sometimes learning out of it, made my day :laugh:
Quote from: SerErris on 16:53, 06 March 22Hmm .. you are right ... I need a pulldown...
Just for info (I know you've gone back to V1): It's better practice to do the reverse the logic, ie: connect the jumpers to GND and add pull-ups.
Bryce.
Quote from: Bryce on 08:24, 07 March 22Bryce.
Good opportunity to improve my electrotech knowledge:
Can you please give me a quick summary on what the benefits are from one ore the other?
One of the main reasons is that you don't want to have the 5V rail on a jumper pin. It oxidises over time and gives a bad connection. This doesn't happen to a pin with GND on it.
Bryce.
Quote from: Bryce on 14:38, 07 March 22One of the main reasons is that you don't want to have the 5V rail on a jumper pin. It oxidises over time and gives a bad connection. This doesn't happen to a pin with GND on it.
Bryce.
Thanks, that makes sense. Will consider that in the future.
Hi all,
I have now build on of the simplified DiagRoms with V1.01 - this is now tested and works as designed.
If anyone wants to build one, here is the schematic and the gerber files.
Also the components list is attached
I do have some of the PCBs here at home, so if you need any, I can ship it for €3+shipping.
Regards
SerErris
Nice done. :)
Ironically, I will be not surprise if it cost less to use the gerber file to order 5 pcs from JLC PCB than asking you to ship one.
If you add a reset button and an enable/disable switch - then you basically have a hackit cartridge - that can be very useful
Quote from: zhulien on 07:25, 13 January 23If you add a reset button and an enable/disable switch - then you basically have a hackit cartridge - that can be very useful
Funny enough: I started exactly the same project last weekend: An alternative LowerRom can be selected with a DIP switch, it can be disabled, has a reset switch and has the option to solder either an MX4 connector or an edge connector.
However I hadn't thought about the solution how to deal with ROM 0 and ROM 7 which I wanted to remain active.
Quote from: SerErris on 16:45, 12 January 23this is now tested and works as designed
The 74HCT02 seems to be brilliant and if I may, I will apply that to my own design. Great work!
Actually V2 should have (never finished it yet) a way to disable the rom also via Software. This is needed by the DiagRom to allow to scan the internal lower rom. This Rom board does not allow to scan the internal lower ROM, as it will be either online or offline.
The issue is, that beeing able to disable it via software it will need a lot more glue logic, including a Flipflop and some other parts to decode the address for activating/deactivating the flipflop.
I think I will reconsider my plans here to make it simplified, but actually not a universal lower rom board, but more like a simplified DiagRom Board.
So the sole purpose is not to be anoter M4 or any other Rom Board, but to be a simple as it could get rom board for the DIAG rom.
Maybe we want to collect some features?
Currently on the backlog:
1. Reset button
2. Exchange the pin header jumper select with a switch for hardware enable/disable of the ROM
3. make it possible to enable/disable via software for the diag rom.
@eto please use it for anything you like
@TotO yes, that looks like it - however it is faster and who needs 5 of those?
Quote from: SerErris on 12:05, 13 January 23however it is faster and who needs 5 of those?
It can be to share PCB into his own city/country or to save shipping fees on parts order to provid assembled boards to friends.
That is true and makes a lot of sense.
In that ballpark - the only reasonable shipping of mine would be within germany via good old letter ... anything else would not be economically wise :-) The shipment alone would have more cost then PCBway or JLCPCB
@SerErris Thank you for this.
Just built one and it is very useful.
Tested on CPC464, CPC6128 and 6128Plus.My Small ROM Board Cropped.jpg