Does CPC use the R-efresh Z80A register?

[McArti0]

Code Select Expand

org #4000
di
ld bc,&bc06
out (c),c
ld bc,&bd00
out (c),c

ld bc,&bc01
out (c),c
ld bc,&bd00
out (c),c

ld ix,0

ld bc,&1
ld a,0
ld de,0
ld hl,10

.loop
add ix,bc
ld r,a
nop
nop
nop
jr nc,loop
ld r,a
sbc hl,de
ld r,a
jr nc,loop

ld bc,&bc06
out (c),c
ld bc,&bd00+25
out (c),c
ld bc,&bc01
out (c),c
ld bc,&bd00+40
out (c),c
halt


[Gryzor]

Two options allowed in the poll? 

[andycadley]

I don't think it does:

See https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/crtc-settings-which-cause-ram-refresh-to-stop/

[McArti0]

Two options allowed in the poll?

Yes.   so that someone can change their mind.

[Bryce]

I'll just leave this here...

It's a paragraph taken from the great book "Understanding And Expanding Your AMSTRAD CPC 464 664 6128" by Alan Trevennor and published by Sigma Press (well worth reading). https://www.cpcwiki.eu/index.php/Understanding_and_Expanding_your_Amstrad_CPC464-664/6128

The entire book can be found in text and PDF format here:

https://archive.org/stream/understanding-and-expanding-your-amstrad-cpc-464-664-6128-alan-trevennoracme/Understanding_and_expanding_your_AMSTRAD_CPC464-664-6128%28Alan_TREVENNOR%29%28acme%29_djvu.txt

"The RAM chips 

The RAM consists of 8 chips. These are all 64K by 1 bit dynamic RAM chips, 
type HM4864. Whilst they offer far higher capacity per chip than a static RAM 
(for example the 6116 RAM which is a 2K by 8 bit, which you may have 
seen used in magazine projects a lot), dynamic RAM chips need to be 
continuously reminded of what they are remembering! This is because the 
memory elements are actually tiny capacitors, which if they are not topped up 
will lose their charge. This top up function is called refreshing them. (No 
Lager jokes please!). The trick is to perform the RAM refresh when the 
memory is not being accessed. In fact the Z80A has the facility to 
automatically perform refresh, but in the CPC the gate array has been chosen 
to do it. This is because the memory is also accessed by the VDU controller, 
and the gate array has to ensure that the memory is not required by either 
processor or VDU controller before refresh can occur. The memory refresh 
process consists of pulsing two input lines to all the RAM chips. These are 
called CAS (Column Address strobe) and RAS (Row address strobe). These 
are pulsed whilst the row and column addresses are passed into the RAM 
sequentially. The 4864 chips used have a cycle time of 200 nanoseconds."

Bryce.

[Gryzor]

Two options allowed in the poll?

Yes.  so that someone can change their mind.

That's another option ("allow users to change their vote" or something), the option you enabled allows users to vote both yes and no at the same time

[McArti0]

But now they won't deny that they pressed NO.   At least I think so

[Bryce]

Why would they want to deny something that I just confirmed above?

Bryce.

[McArti0]

Because the code I showed shows that if you turn off the CRTC counter and turn off R, refreshing does not occur. 

But if we do not turn off R, refreshing works great, for all memory. Why? 

Because the memory is refreshed based on R from Z80 and the RAS signal in RAS-only memory mode.

And this happens for 60% of the time CPC is running in standard resolution.

Ps. Additionally, it is a surprise that in LowROM there are LD R,A and LD A,R commands, and more than once.

[eto]

But if we do not turn off R, refreshing works great, for all memory. Why?

Did you check "CRTC off, but R active" where your test code disables all interrupts, disables the CRTC and then enters an endless loop?

[McArti0]

where your test code disables all interrupts, disables the CRTC and then enters an endless loop?

On my CPC . I will prepare such a comparison on DSK.
The code shown is spectacular because it shows the contents of unrefreshed memory.

[Bryce]

The CRTC is creating the addresses for the refresh, so any changes to the CRTC could effect the refreshing.

Bryce.

[McArti0]

R6=0 R1=0 and CRTC nothing creating. When always set R=0 CPC crashing. When R is working CPC without CRTC working too.

[eto]

I might be wrong but when I made my internal RAM expansion I this became my understanding of the refresh, which was the foundation to actually replace the internal RAM with bigger ICs:

The 4164 ICs are organized as a matrix of 128 rows and 512 columns of cells(bits). These cells need to be refreshed every 2ms at least. Each 512 cells in a row are refreshed, when the respective row is accessed (RAS signal + address lines). So what a computer needs to ensure is that within 2ms all 128 RAM rows are accessed at least once. It's not necessary to really read from RAM, it's just important that the RAS signal is there and 128 different ROW addresses have been accessed within those 2ms.  How the computer is doing that is is done is not relevant. You can use the RFSH signal to build a respective circuit that does that - or you can do it differently. Any access to the RAM will refresh cells and as long as you make sure all rows are accessed your RAM will be refreshed.

The Amstrad engineers now did quite a genius trick which ensures RAM refresh as a side effect of the GateArray accessing the RAM, which it will always do (unless someone explicitly disables it):

The lower address lines A0-A7 of the memory are usually mapped to the CAS sequence of RAM access, but in the CPC they are mapped to the RAS sequence. (Note: The higher lines A8-A15 are then mapped to the CAS sequence. For the physical storage in the RAM ICs this doesn't matter how exactly the bytes are stored as long as reads and writes to the same address also access the same byte in RAM.)

This unusual physical addressing has a nice side effect for RAM refresh: As long as RAM is accessed byte per byte for at least 128 bytes continuously all RAM rows will be refreshed properly - without the need for any special refresh logic.

And exactly this is, what the GateArray does as it accesses the screen RAM byte by byte for usually 16KB in a row. And as long as the GateArray reads the screen the RAM will be refreshed.

If you now turn off the GateArray access it doesn't necessarily mean that the RAM will no longer be refreshed as also CPU access to the RAM will also refresh the RAM. Again as long as the CPU reads from 128 continuous addresses (within the refresh period of 2ms) all RAM rows will be accessed - and refreshed. If I am not mistaken this does even work if the CPU reads from ROM as the address will be put on the RAM IC address pins during the RAS sequence - just the CAS is not executed - but that doesn't matter as only RAS is required to do the RAM refresh.

So as long as the computer is accessing "enough" bytes within the 2ms refresh window the RAM rows will be refreshed.

[eto]

On my CPC . I will prepare such a comparison on DSK.

Sorry, I did not mean "where" you did that. But you need to compare both situations similarly: 

When you set the R-register to the same value you are doing that in an endless loop. When you do the same check without setting the R register you need to use the exact same code that disables the CRTC and goes into an endless loop (just not set the R register). 

[McArti0]

YES!    eto win. Long 7ms between last screen line  no. 200 to first line no. 0,  memory is refreshing by z80 and his R register.

[SerErris]

I try to answer it in a different way.

No the CPC in any normal operation never needs or considers the refresh register. Also the Gatearray is very closely managing the access to the ram.

How does the refresh work on a 4864 ?
If you put an address (8bit) to the RAM chip, and then strobe RAS signal, it will read the whole row into a buffer and writes it back into the cell. That is actually the refresh.

So if you do read every row through the required time, then the CPU putting addresses to the bus, would not be required.

However obviously with normal code, you cannot guarantee, that the CPU just by chance is reading all rows.

So that is (we are now forgetting about the CPC for a second here), why the CPU supports to output addresses to the addressbus, when it actually does not need it and then run the refresh with that. This would be required in other systems, as nothing else would read the RAM.

However in CPC, the CRTC is connected to the RAM in a way, that it output each of the 256 row addresse for every frame. So the refresh will be done every 20µs.

Also the Gatearray is handling the access of the Addressbus to the RAM. At CPU T-Cycles 3 and 4 (3 and 4 are normally the normal refresh cycle) the gatearray exclusively reserves the RAM access to the CRTC and Gatearray. CRTC is actually not reading it, but outputting the correct memory address.

Gatearray will read actually data in that timeframe.

So even if you would want to believe that the CPU refresh is doing anything, it is actually not able to ever output the address to the physical ram as it is blocked via the Multiplexer by command of the GateArray.

The GateArray is actually the Commander in the CPC  - not the CPU. The CPU needs to obey to the ruling of the GateArray.

[SerErris]

Some more background, from Z80 User Manual:

Memory Refresh (R) Register. The Z80 CPU contains a memory refresh counter, enabling dynamic memories to be used with the same ease as static memories. Seven bits of this 8-bit register are automatically incremented after each instruction fetch. The eighth bit remains as programmed, resulting from an LD R, A instruction. The data in the refresh counter is sent out on the lower portion of the address bus along with a refresh control signal while the CPU is decoding and executing the fetched instruction. This mode of refresh is transparent to the programmer and does not slow the CPU operation. The programmer can load the R register for testing purposes, but this register is normally not used by the programmer. During refresh, the contents of the I Register are placed on the upper eight bits of the address bus.

Here is the corresponding timing diagram:
You cannot view this attachment.

So you can see, refresh is working in T-Cycles 3 and for of an M1 cycle (opcode fetch). 

Two other things to notice:
1. The RFSH line is not connected to any component in the CPC, only to the external bus. That would be needed, as if you do not strobe the RAS signal, you will not get the RAM to read anything into the buffer and therefore not being able to refresh it. Some extra logic is required to use that feature.
2. See the Gatearray timing, that exclusively openes a Window for the addresses of the CPU getting to the RAM.

Pls see the attached diagram. I shamelessly copied it from here https://bread80.com/2021/06/03/understanding-the-amstrad-cpc-video-ram-and-gate-array-subsystem/:

Blue is, the gatearry is using the RAM, red is, when the Gatearray is actually alowing the CPU to read from ram. But control (RAMRD and CPU line) is handled by the GateArray.

You cannot view this attachment.

[McArti0]

All incorrect. T4 is for CPU. and CPU refresh work.

[SerErris]

You are saying Zylog is incorrect about their timing? 

Read it yourself if you do not trust me copying it from the original manual.
https://www.zilog.com/docs/z80/um0080.pdf

I know you know better than anyone before you. We are all wrong.

[McArti0]

ETO win this competition. Do not get excited. Write next post tomorrow ok?

Winner text:

Quote from: eto on 12.03.2024, 16:39:51
If you now turn off the GateArray access it doesn't necessarily mean that the RAM will no longer be refreshed as also CPU access to the RAM will also refresh the RAM. Again as long as the CPU reads from 128 continuous addresses (within the refresh period of 2ms) all RAM rows will be accessed - and refreshed. If I am not mistaken this does even work if the CPU reads from ROM as the address will be put on the RAM IC address pins during the RAS sequence - just the CAS is not executed - but that doesn't matter as only RAS is required to do the RAM refresh.

[eto]

memory is refreshing by z80 and his R register.

no, it's not... that's what I tried to explain in my very long post (and what SerErris also explained in a different way): The r register does not have anything to do with the RAM refresh in the CPC. 

You can also check the schematics to see that the RFSH line of the CPU is not used anywhere in the CPC (except for the expansion bus).

[eto]

ETO win this competition. Do not get excited. Write next post tomorrow ok?

Winner text:

Quote from: eto on 12.03.2024, 16:39:51
If you now turn off the GateArray access it doesn't necessarily mean that the RAM will no longer be refreshed as also CPU access to the RAM will also refresh the RAM. Again as long as the CPU reads from 128 continuous addresses (within the refresh period of 2ms) all RAM rows will be accessed - and refreshed. If I am not mistaken this does even work if the CPU reads from ROM as the address will be put on the RAM IC address pins during the RAS sequence - just the CAS is not executed - but that doesn't matter as only RAS is required to do the RAM refresh.

but it's not the refresh feature of the CPU. This will only happen if the CPU "coincidentally" accesses the right addresses. And this coincidence is pretty high in the CPC as A0-A7 are connected to the RAM rows.

[SerErris]

It is actually the loop you are running to test it.

Every read of the memory (so actually the loop) will read that row (the whole row). And this row will get refreshed. Your loop will have some bytes, which translates into memory rows (as ETO explained).

So if you are running aloop over a few bytes (lets say 10) you will already hit 10 rows in the CPC. If your loop is running over 127 bytes - you probably hit all rows.

So the loop itself will never recognize that anything is wrong as the loop itself does refresh the cells needed for the loop (and others).

[eto]

is running over 127 bytes - you probably hit all rows.

if it runs over 128 bytes it will definitely hit all rows.

memory is refreshing by z80 and his R register.

Maybe another test you can do: Remove the Z80 from its socket. Bend up the RFSH pin and put the CPU back into its socket. Then try again.