As I tell you in my presentation topic, I'm making with a group of friends a megaflash interface, but modifying the layout to be able to use a specific box.
In my version I have used a EDGE conector directly to the PCB, and is possible to choose use a SMD, or DIP flash memory, at your choice.
Now I have the first interface built and I want to show you the results.
The idea is to remove the led and the switch from the PCB and install them in the box, to let the access with the box closed, but now is totally operative.
First the board design:
(https://lh4.googleusercontent.com/--SrHwH5n65M/UjCc22oXN1I/AAAAAAABUWM/4akRZQjR9s8/w564-h324-no/MEGAFLASHROM.png) (https://lh4.googleusercontent.com/--SrHwH5n65M/UjCc22oXN1I/AAAAAAABUWM/4akRZQjR9s8/w564-h324-no/MEGAFLASHROM.png)
Now the board result.
(https://lh3.googleusercontent.com/-hxc0urPETKg/UlbDQ20e53I/AAAAAAABV-w/-G8duVLAZ6g/w1113-h835-no/PIC_2695.JPG) (https://lh3.googleusercontent.com/-hxc0urPETKg/UlbDQ20e53I/AAAAAAABV-w/-G8duVLAZ6g/w1113-h835-no/PIC_2695.JPG)
(https://lh3.googleusercontent.com/-8jk0M8Mun60/UlbDTXWr4rI/AAAAAAABV_c/fhcv5bIf5Cw/w1127-h835-no/PIC_2694.JPG) (https://lh3.googleusercontent.com/-8jk0M8Mun60/UlbDTXWr4rI/AAAAAAABV_c/fhcv5bIf5Cw/w1127-h835-no/PIC_2694.JPG)
The interface without box:
(https://lh6.googleusercontent.com/-2SJxqWv6Ykw/Ulqw9WaMG_I/AAAAAAABWF4/NpkhB-CibQY/w507-h380-no/PIC_2716.JPG) (https://lh6.googleusercontent.com/-2SJxqWv6Ykw/Ulqw9WaMG_I/AAAAAAABWF4/NpkhB-CibQY/w507-h380-no/PIC_2716.JPG)
(https://lh6.googleusercontent.com/-LfmDyBtlGOU/Ulqw_XDc7_I/AAAAAAABWGA/q0yQZol18Uw/w507-h380-no/PIC_2717.JPG) (https://lh6.googleusercontent.com/-LfmDyBtlGOU/Ulqw_XDc7_I/AAAAAAABWGA/q0yQZol18Uw/w507-h380-no/PIC_2717.JPG)
With box:
(https://lh4.googleusercontent.com/-TUshk1wS5Ho/UlqxB2pEjVI/AAAAAAABWGM/j34RHWUvWwU/w507-h380-no/PIC_2718.JPG) (https://lh4.googleusercontent.com/-TUshk1wS5Ho/UlqxB2pEjVI/AAAAAAABWGM/j34RHWUvWwU/w507-h380-no/PIC_2718.JPG)
(https://lh3.googleusercontent.com/-UogxNUyBMjE/UlqxCFhqgwI/AAAAAAABWGU/KySY_UNfiT8/w507-h380-no/PIC_2719.JPG) (https://lh3.googleusercontent.com/-UogxNUyBMjE/UlqxCFhqgwI/AAAAAAABWGU/KySY_UNfiT8/w507-h380-no/PIC_2719.JPG)
(https://lh6.googleusercontent.com/-jM4HNvzgvcA/UlqxC--ukiI/AAAAAAABWGY/x5mVPi33Ctk/w507-h380-no/PIC_2720.JPG) (https://lh6.googleusercontent.com/-jM4HNvzgvcA/UlqxC--ukiI/AAAAAAABWGY/x5mVPi33Ctk/w507-h380-no/PIC_2720.JPG)
Starting with the interface connected;
(https://lh5.googleusercontent.com/-V8dXivetxYo/UlqxHQPnucI/AAAAAAABWGo/1t0rpC-fk-8/w507-h380-no/PIC_2721.JPG) (https://lh5.googleusercontent.com/-V8dXivetxYo/UlqxHQPnucI/AAAAAAABWGo/1t0rpC-fk-8/w507-h380-no/PIC_2721.JPG)
Handling the interface with ROMAN
(https://lh6.googleusercontent.com/-Xa8aGtioDYk/UlqxHVKM_XI/AAAAAAABWGs/3MC6Te7mIXk/w507-h380-no/PIC_2722.JPG) (https://lh6.googleusercontent.com/-Xa8aGtioDYk/UlqxHVKM_XI/AAAAAAABWGs/3MC6Te7mIXk/w507-h380-no/PIC_2722.JPG)
Write mode:
(https://lh5.googleusercontent.com/-Vo6-N6i4m1k/UlqxH_kRslI/AAAAAAABWGw/RNoxg4nTJXs/w507-h380-no/PIC_2723.JPG) (https://lh5.googleusercontent.com/-Vo6-N6i4m1k/UlqxH_kRslI/AAAAAAABWGw/RNoxg4nTJXs/w507-h380-no/PIC_2723.JPG)
All is working right, except for the initialization (unprotect) of the chip. It is not working from ROMAN and is not working from MegaFlash ROM Manager either.
I have to unprotect the chip from the EPROM programmer.
Somebody have any idea what is happening?
Very nice! :)
Nice that you have the choice of dip or plcc flash chip. You could have made it so the DIP socket could be cut off if you fitted the plcc chip.
I'm suprised you bothered with a ziff socket, does it need to come out that often?
Quote from: wilco2009 on 20:06, 13 October 13
All is working right, except for the initialization (unprotect) of the chip. It is not working from ROMAN and is not working from MegaFlash ROM Manager either.
I have to unprotect the chip from the EPROM programmer.
So is it just the unprotect that doesn't work. Once unprotected in your eprom programmer you can flash individual roms?
What a great mod. Really nicely done. Very nice of you to mention me on the board too :)
Bryce.
Quote from: IanS on 20:18, 13 October 13So is it just the unprotect that doesn't work. Once unprotected in your eprom programmer you can flash individual roms?
Quote from: IanS on 20:15, 13 October 13
Nice that you have the choice of dip or plcc flash chip. You could have made it so the DIP socket could be cut off if you fitted the plcc chip.
I'm suprised you bothered with a ziff socket, does it need to come out that often?
Yes, once unprotected I can write roms without problems.
ZIF socket is mainly for 464 users.
By other hand, I hope it will be not used as often as now in the future, but now I'm plugging and unplugging the chip many often to do trials
Quote from: Bryce on 20:42, 13 October 13
What a great mod. Really nicely done. Very nice of you to mention me on the board too :)
Bryce.
Many thanks Bryce. :D
Why did you go for a soldered PLCC footprint instead of Socket? Or will an SMD PLCC socket fit there? It looks a bit too tight to fit.
Bryce.
Quote from: wilco2009 on 20:51, 13 October 13
Yes, once unprotected I can write roms without problems.
If you read the flash chip in your eprom programmer does the data look ok? Do the roms appear at the right address within the flash? (I'm wondering if any of the data or address lines are mixed up, if they were the commands and addresses used for the unprotect command would be wrong)
If any of the address or data lines were mixed up, then it wouldn't work as a ROMBoard at all. At least not for the ROMs he had written with the EPROM Programmer.
Bryce.
Quote from: Bryce on 20:55, 13 October 13
Why did you go for a soldered PLCC footprint instead of Socket? Or will an SMD PLCC socket fit there? It looks a bit too tight to fit.
Bryce.
ZIF socket is something optional. Some guys ask me to include one and other not. With a ZIF socket installed there are no room to install a PLCC socket, but with a standard socket you can install both.
Quote from: IanS on 20:58, 13 October 13If you read the flash chip in your eprom programmer does the data look ok? Do the roms appear at the right address within the flash? (I'm wondering if any of the data or address lines are mixed up, if they were the commands and addresses used for the unprotect command would be wrong)
Quote from: Bryce on 21:08, 13 October 13
If any of the address or data lines were mixed up, then it wouldn't work as a ROMBoard at all. At least not for the ROMs he had written with the EPROM Programmer.
Bryce.
Exactly. It works with a flash (or EPROM) programmed with a EPROM programmer without problems.
ROMs can be written from the disk to the interface with ROMAN or MEGAFLASH ROM Manager perfectly.
The only thing I can't do from the interface is unprotect the chip.
Quote from: wilco2009 on 21:34, 13 October 13
ZIF socket is something optional. Some guys ask me to include one and other not. With a ZIF socket installed there are no room to install a PLCC socket, but with a standard socket you can install both.
I understood that bit. I actually thought that a PLCC socket might hit IC3? That looks close.
Bryce.
Quote from: Bryce on 21:08, 13 October 13
If any of the address or data lines were mixed up, then it wouldn't work as a ROMBoard at all. At least not for the ROMs he had written with the EPROM Programmer.
Bryce.
I agree, but at the time I made the comment he never said he'd written any roms from his eprom programmer, I could only see a comment about unprotecting it with his epron programmer.
Actually if A14 and above were mixed up, the roms would work but appear out of order, but the unprotect command wouldn't work.
Does the rom written at &4000 via the eprom programmer appear as rom 1 on the CPC?
Quote from: IanS on 21:47, 13 October 13
I agree, but at the time I made the comment he never said he'd written any roms from his eprom programmer, I could only see a comment about unprotecting it with his epron programmer.
Actually if A14 and above were mixed up, the roms would work but appear out of order, but the unprotect command wouldn't work.
Does the rom written at &4000 via the eprom programmer appear as rom 1 on the CPC?
I don't think so, but I'm not sure.
I will check it and I'll tell you the results.
Quote from: wilco2009 on 21:38, 13 October 13
The only thing I can't do from the interface is unprotect the chip.
Yes, my ROManager can do that. But you need ROM 0 be switched active when performing that task. Take a look at the manual. :)
Very nice project !
Quote from: wilco2009 on 22:42, 13 October 13I don't think so, but I'm not sure.I will check it and I'll tell you the results.
The order is totally right in the 32 positions.
Quote from: TFM on 00:05, 14 October 13
Yes, my ROManager can do that. But you need ROM 0 be switched active when performing that task. Take a look at the manual. :)
Oh!!!, It will be the problem!!, I have ROM 0 inactive. :)
I'll try it and tell you.
Quote from: TFM on 00:05, 14 October 13
Yes, my ROManager can do that. But you need ROM 0 be switched active when performing that task. Take a look at the manual. :)
I understand why that's the case, but it doesn't have to be. The 29c040 datasheet is inconsistant, but my testing confirms that it only takes A0-A14 into account for the command addresses, so when you think you need to select rom 0 for the appropriate address, you can also select any rom where A14 (thats D0 of the rom number) = zero. Does that make sense?
Quote from: Bryce on 21:40, 13 October 13
I understood that bit. I actually thought that a PLCC socket might hit IC3? That looks close.
Bryce.
In the picture, you can see, if you use a convencional socket, you can install both chips at once.
(https://lh6.googleusercontent.com/-YXPft4Dd5Es/Ulw66TGrQrI/AAAAAAABWS0/j8Pt0QCivjw/w1056-h792-no/20131014_193033.jpg)
In any case, my initial idea is to choose the technology at manufacture time. In this case you only install one of them.
But could be useful if you install both simultaneously in case of you have chips of both technologies.
Quote from: TFM on 00:05, 14 October 13Yes, my ROManager can do that. But you need ROM 0 be switched active when performing that task. Take a look at the manual. :)
Mistery solved, the problem was ROM0 has to be active.
Everithing is working right now.
Thank you very much to everybody.
Quote from: IanS on 17:58, 14 October 13
I understand why that's the case, but it doesn't have to be. The 29c040 datasheet is inconsistant, but my testing confirms that it only takes A0-A14 into account for the command addresses, so when you think you need to select rom 0 for the appropriate address, you can also select any rom where A14 (thats D0 of the rom number) = zero. Does that make sense?
A14 or A15 ??
So instead of ROM 0 you could select ROM 128 ??
Quote from: TFM on 21:28, 14 October 13
A14 or A15 ??
So instead of ROM 0 you could select ROM 128 ??
The flash chip is 512KB device, which has address pins A0 to A18, 19 address pins. A0 to A13 (14 pins 16K) are driven directly from the address pins of the CPC. The top 5 pins are driven from a latch that is loaded when the rom number is selected. So bit 0 of the rom number drives A14 of the flash chip (bit 1->A15 bit 2->A16 etc.)
Only address pins A0-A14 of the flash chip need to be set correctly for the protect/unprotect commands to work. So if you select any rom number where bit 0 of the romnumber is zero (e.g. 2,4,6 or any even number) it should be ok.
So the two address used by the protect/unprotect commands are:-
5555 = Rom 1 (A14=1) cpc address = D555
2AAA = Rom 2 (A14=0) cpc address = EAAA
Any clearer?
Aehm... still sick at home with the flu. But thanks' for the explanation! Now I ask if this does work with all Flash chips? Can somebody confirm with real hardware?
That only work with Winbond compatible chip. We use that on the CTC-AY cartridges.
So, better to read the datasheet in all cases. ;)
Quote from: TotO on 09:46, 16 October 13
That only work with Winbond compatible chip. We use that on the CTC-AY cartridges.
So, better to read the datasheet in all cases. ;)
Alright. To be at the safe side I leave all like it is and the user has to switch on ROM 0. And why not? It usually contains a copy of the real ROM 0 (or an advanced version). So no reason to keep it OFF.
However I may add a 'Flash-manufacturer ID recognizer' one day and then this knowledge may be beneficial.
Thanks' to everyone for your comments. Very interesting. :)
Quote from: TFM on 19:09, 16 October 13
Alright. To be at the safe side I leave all like it is and the user has to switch on ROM 0. And why not? It usually contains a copy of the real ROM 0 (or an advanced version). So no reason to keep it OFF.
However I may add a 'Flash-manufacturer ID recognizer' one day and then this knowledge may be beneficial.
The 39sf040 works in similar way, it's what I do with my flash rom board. (The data sheet says that the address is only read from A0-A14 and that A15-A19 need to be all 1 or all 0, but that doesn't seem to be the case on chips I've tried).
I don't think the megaflash design supports reading the Flash-ID, as you can't read from the flash chip when in write mode.
Oh, well, I have to find out with real hardware. They told me before that the CPC can't switch the SDP on or off, and now ROManager can do it. So maybe there is a way.
Me likey. Very tidy, and a substantial improvement if you only use MegaFlash!
After some time working with my Megaflash interface I have found a very curious problem.
Firstly I had copied, internal AMSDOS ROM to ROM7 and everything has been working right until now.
Yesterday I tried to install a diferent Disk OS in ROM7. I tryied with RODOS first and AMDOS 0.7 after, and I get a corrupt name in ROM7 and a non working Disk OS ROM.
If I read the content of the flash memory with my EPROM programmer the content of the ROM7 match exactly with the file copied (RODOS or AMSDOS 0.7).
Due to it, I know my interface is working right writing ROM7, then it have to be not working reading ROM7.
By other hand, if I copy internal ROM to ROM7 then my Megaflash works right. Due to it, I think the CPC is reading partially internal ROM and partially ROM7, mixing the content.
Additionally, all other ROMs (including ROM0) are working right in reading and writting.
I was measuring continuity comparing with the schema, and I was comparing my schema with Bryce schema and everithing seems correct. (Of course something is wrong)
Somebody could have some idea about what could be the problem?
This is expected ;D
On a 6128/664 or 464+DDI1, ROM 7 cannot be masked by an external rom expansion without a HW modification on the CPC (or DDI1).
More there : Disabling ROM 7 (http://www.cpcwiki.eu/forum/amstrad-cpc-hardware/disabling-rom-7/)
Thanks a lot. You have saved me a lot of hours with the multimeter. ;D
Quote from: gerald on 18:19, 21 October 13
This is expected ;D
On a 6128/664 or 464+DDI1, ROM 7 cannot be masked by an external rom expansion without a HW modification on the CPC (or DDI1).
More there : Disabling ROM 7 (http://www.cpcwiki.eu/forum/amstrad-cpc-hardware/disabling-rom-7/)
Disabling the internal disk rom also discissed here - Disable Disc ROM (http://www.cpcwiki.eu/forum/amstrad-cpc-hardware/disable-disc-rom/)
Basically linking pin 13 (or any of the connected tracks ) of IC210 to GND will stop the internal rom from ever being selected.
With a big 512K ROM board, what is the interest to disabling ROM7?
Putting PARADOS on ROM6 and it's done. No?
Yes, but I tried to put ROMDOS for example.
I'm a newbie in CPC matters and I'm not sure if I'll need to patch ROM7 in any case.
I have never tried ROMDOS. It not work in ROM6?
No it doesn't.There are a lot of DOS ROMS only working on ROM7. See ROM List - CPCWiki (http://cpcwiki.eu/index.php/ROM_List)
Enhanced DOS ROMs working fine at positions 2-7 (1 shall be reserved for the RAMdisc ROM RDOS from Dobbertin) are VDOS and X-DDOS and probably others.