MEGAFLASH PLUS SX

[wilco2009]

Hi guys!

I'm sure that all of you know the Megaflash from Bryce.

Some time ago I made a new board with different layout but using the same scheme.

Based on the study of this schema and the knowledge contained in the wiki I have designed a new improved version of the megaflash with the following differences:

- It is possible to include lowerROMs in the flash chip. Now position 7 is reserved to include a lowerROM (in the same way that XMEM card from cent pour cent). Now the CPC can start with this lowerROM together with the ROM0 contained in the flash memory.
A second lowerROM/BasicROM set can be selected using slots 30 & 31.

- Footprints for MX4 and EDGE connectors are included.

- A IDC26 connector is included to connect directly my multisystem floppy controller.

I'll make a short batch of it soon. Price will be around 20€ in kit format and 25€ assembled plus shipping costs.


If you want to make it by your self, I will publish all the necessary information here.

Bellow you can find some pictures of the board, being used with the floppy controller.


The board:





Starting with an alternative lowerROM






Connected to my Multypurpose floppy controller.








I hope you like. 



NECESARY FILES TO ASSEMBLE THE INTERFACE


Final board will be as follows





Schematics

Click here to enlarge image

GERBER Files
EAGLE Files
JED File
GAL sources in ABEL
Partlist

GAL Equations:

ROM_NO_OE     = (  NO_ROMEN );


ROMA14     = (  A15 & D0
              #   !A15 & !LOWER_ROM_SELECTED
              #   A15 & !D5_o_D6_o_D7 & !D4 & !D3 & !D2 & !D1
                & LOWER_ROM_SELECTED & !INT_LOWROM_ENAB );


ROMA15     = (  !A15
              #   D1
              #   !D5_o_D6_o_D7 & !D4 & !D3 & !D2 & !D0 & LOWER_ROM_SELECTED
                & !INT_LOWROM_ENAB );


ROMA16     = (  !A15
              #   D2
              #   !D5_o_D6_o_D7 & !D4 & !D3 & !D1 & !D0 & LOWER_ROM_SELECTED
                & !INT_LOWROM_ENAB );


ROMA17     = (  A15 & D3
              #   !A15 & LOWER_ROM_SELECTED
              #   !D5_o_D6_o_D7 & !D4 & !D2 & !D1 & !D0 & LOWER_ROM_SELECTED
                & !INT_LOWROM_ENAB );


ROMA18     = (  A15 & D4
              #   !A15 & LOWER_ROM_SELECTED
              #   !D5_o_D6_o_D7 & !D3 & !D2 & !D1 & !D0 & LOWER_ROM_SELECTED
                & !INT_LOWROM_ENAB );


ROMDIS     = !(  !A15 & INT_LOWROM_ENAB
              #   A15 & D5_o_D6_o_D7 & WRITE_DISABLE
              #   A15 & !D4 & !D3 & D2 & D1 & D0 & WRITE_DISABLE
              #   !D4 & !D3 & !D2 & !D1 & !D0 & INT_LOWROM_ENAB & WRITE_DISABLE );


ROM_NO_CE     = (  !A15 & INT_LOWROM_ENAB
                 #   A15 & D5_o_D6_o_D7 & WRITE_DISABLE
                 #   A15 & !D4 & !D3 & D2 & D1 & D0 & WRITE_DISABLE
                 #   !D4 & !D3 & !D2 & !D1 & !D0 & INT_LOWROM_ENAB
                   & WRITE_DISABLE );


ROM_NO_WE     = !(  A15 & !WRITE_DISABLE & !NWR
                 #   !INT_LOWROM_ENAB & !WRITE_DISABLE & !NWR );

I add some additional comments about the assembly and the use of the switches bellow.

I have started to send packets, but I have a problem with the IDC connectors. Provider have sent me connectors with straight pins instead connectors with right angle pins. He has re-sent them.
- In the board R4 is 4k7 but I have changed it to 1K. It is due to the fact I have used a 74HC374 in the prototype, but the chips I bought for the kids are 74LS374. I thought it will have not any influence but, it has not been so.

- Switches are a model for pcb. To use it in the box supplied you can used two different methods:

1. Led and switches installed in the top of the box. To do that you can weld the switches on the surface as a SMD component.





For the SPDT switch we can insert a bit the three pins of the bottom side and use a straight pins row, to weld the three pins of the top (see the picture).





Once the board is mounted, you have to make the holes in the top of the box to permit the access.

2. You can install all the selectors and led in the bottom side of the board.

In this case you have to make the holes for the switches in the back side of the box.

JP3 is just to disable the interface. It is not necessary to access from outside the box. If you need to use it you can open the box to access.

USE OF THE SWITCHES.

We have a total of 4 switches in the board. I will describe their funcionality looking from the front of the CPC with the interface connected.

JP2: At the top right. Initially it could be used to select lower ROM 0 or 1 in the flash memory. Now it has no use, but I left it there for futures updates.

JP1: Used to activate internal (CPC) or external (interface) lowerROM. To the left external lowerROM is selected.

S1: Used to activate the write mode. To avoid corrupting the flash memory is important to keep it at left (LED off) except of when it is required by the system.

JP3: It is located at the bottom right and it is Used to deactivate the interface. Interface is active when the switch is at top. To deactivate the interface JP3 have to be at bottom and JP1 to the right.

The GAL is already programmed with the correct equations and the flash memory is burned with a starting up set of ROMs and unprotected.


Flash memory have installed ROMAN, and a 64Kb version of the TFM's Megaflash ROM manager (it starts with MODE 2:|rme)

Flash memory have installed a 6128 lowerROM modified to intialize 32 ROMs and their corresponding BASIC.

I'm sorry for my English.

Below you can find pictures of the MX4 version. It is important to take care with the connector position.


Connected to the CPC....



Unconected....



From the other side...





A detail of the connector from bottom. Look the right side cutted to make room to the resistor and diode.

[Audronic]

Looks Good


I have sent a PM about Purchasing 1 Megaflash Plus SX.
Please put me on the list

Thanks    Ray

[wilco2009]

Looks Good


I have sent a PM about Purchasing 1 Megaflash Plus SX.
Please put me on the list

Thanks    Ray

OK, Audronic.


I'll send you the details by private.

[wilco2009]

Added all the necessary information to build the board.

[Bryce]

Nice use of diodes to reduce part count.

Bryce.

[wilco2009]

Nice use of diodes to reduce part count.

Bryce.

Thanks Bryce.

[wilco2009]

I afraid that I found a bug in the GAL equations of my Megaflash SX. I have been working some time in it but it is not solved yet.


The bug consists on some random writes in not correct places. After some time of work, writing, erasing etc, the content of the flash will be corrupted.


As I said I have made some progress but is not solved yet.


Until now, two people have paid the kit. If in a week I have not found a solution, I'll return them the money and I'll collect the money again when the problem have been solved.


Anyway, because the list is there, I'll keep with the list of the people interested in the project.


Now we are 23 (24 with my kit). Due to it left 6 kits to fulfil a batch of 30 kits.

[wilco2009]

I have found a solution to solve the problem and the interface is now operative.


To use two lowerROMs were not possible because, when I added the equations the Megaflash, it sometimes was writting in incorrect places.
   
Then, the Megaflash SX will store only one lowerROM.


The second selector will be used to deactivate the interface in the startup. It could be usefull in case of corruption of the flash memory. You could populate it  again from disk.


Due to it I can say we can follow with the project.


If anybody would want to be removed from the list because the lack of the second lowerROM, please let me know it.

[wilco2009]

I add some additional comments about the assembly and the use of the switches bellow.


I have started to send packets, but I have a problem with the IDC connectors. Provider have sent me connectors with straight pins instead connectors with right angle pins. He has re-sent them.
- In the board R4 is 4k7 but I have changed it to 1K. It is due to the fact I have used a 74HC374 in the prototype, but the chips I bought for the kids are 74LS374. I thought it will have not any influence but, it has not been so.


- Switches are a model for pcb. To use it in the box supplied you can used two different methods:


1. Led and switches installed in the top of the box. To do that you can weld the switches on the surface as a SMD component.




For the SPDT switch we can insert a bit the three pins of the bottom side and use a straight pins row, to weld the three pins of the top (see the picture).



Once the board is mounted, you have to make the holes in the top of the box to permit the access.




2. You can install all the selectors and led in the bottom side of the board.


In this case you have to make the holes for the switches in the back side of the box.


JP3 is just to disable the interface. It is not necessary to access from outside the box. If you need to use it you can open the box to access.


USE OF THE SWITCHES.


We have a total of 4 switches in the board. I will describe their funcionality looking from the front of the CPC with the interface connected.


JP2: At the top right. Initially it could be used to select lower ROM 0 or 1 in the flash memory. Now it has no use, but I left it there for futures updates.


JP1: Used to activate internal (CPC) or external (interface) lowerROM. To the left external lowerROM is selected.


S1: Used to activate the write mode. To avoid corrupting the flash memory is important to keep it at left (LED off) except of when it is required by the system.


JP3: It is located at the bottom right and it is Used to deactivate the interface. Interface is active when the switch is at top. To deactivate the interface JP3 have to be at bottom and JP1 to the right.


The GAL is already programmed with the correct equations and the flash memory is burned with a starting up set of ROMs and unprotected.


Flash memory have installed ROMAN, and a 64Kb version of the TFM's Megaflash ROM manager (it starts with MODE 2:|rme)


Flash memory have installed a 6128 lowerROM modified to intialize 32 ROMs and their corresponding BASIC.


I'm sorry for my English.

[TFM]

Thanks for the update. There is a newer version of my ROManager at www.futureos.de  If somebody does use it please make a picture and post it here, so I can see which Flash is installed and (if needed) extend the ROManager for new features.

[wilco2009]

Below you can find pictures of the MX4 version. It is important to take care with the connector position.


Connected to the CPC....



Unconected....



From the other side...





A detail of the connector from bottom. Look the right side cutted to make room to the resistor and diode.

[TotO]

Nice, but... Why the parts are not on the other side?
It will not be possible to fit more than 3 boards on the MotherX4, except is the passthrough connector is not used.

[wilco2009]

Nice, but... Why the parts are not on the other side?
It will not be possible to fit more than 3 boards on the MotherX4, except is the passthrough connector is not used.

It is because the board is the same for the EDGE connector and the IDC connector. The EDGE connector sets the order of the holes.


Allways it is possible to use the last connector. Then you can use 4 boards.

[Bryce]

??  It would have easily been possible to put the connector on the other side and still be compatible with a stand-alone connector.

Bryce.

[wilco2009]

??  It would have easily been possible to put the connector on the other side and still be compatible with a stand-alone connector.

Bryce.

If you put the connector on the other side, upper row in the interface is connected to bottom row in CPC and viceversa, for instance pin 1 is connected to pin 2 and viceversa

Or do you mean another thing?

[Bryce]

If you put the connector on the other side, upper row in the interface is connected to bottom row in CPC and viceversa, for instance pin 1 is connected to pin 2 and viceversa

Or do you mean another thing?

Only because you laid it out that way. All other cards have managed to put the connector and components on the same side and still be compatible with a normal flat cable too.

Bryce.

[wilco2009]

Only because you laid it out that way. All other cards have managed to put the connector and components on the same side and still be compatible with a normal flat cable too.

Bryce.

The same board is compatible with EDGE and IDC connectors.
If you put the EDGE connector in components side, then components are facing the  CPC, and it is not possible to connect them right.


Look at the pictures....

[Bryce]

Ah, I didn't realise you had made it edge compatible too!

Bryce.

[Audronic]

Oops
How do I reset the Flash Memory ?


Ray

[wilco2009]

Oops
How do I reset the Flash Memory ?


Ray

To initialise the flash memory you can run ROMAN from disk.


From the main screen enter in the System Menu pressing "y"


Then you can erase the entire flash memory pressing option 4.


Once you have deleted all the memory, you can populate again the memory with the ROMAN it self.


When you finish, could be interesting to protect the flash with the option "1" in the system menu. (remember to unprotect again, option 2, when you need to populate with new ROMs).
For this operation you will need full access to the flash memory, then you will have to change the lowerROM switch and the write switch when CPC ask you to change to write mode.


REMARKS:
To install the lowerROM you have to save the desired lowerROM in the slot 7. When the program ask you to change the swith to write mode then you have to change both (write switch and lowerROM switch), and return to their original position when CPC ask for turn off the write mode.
LowerROM is not showed, but it is there.
To start with the new lowerROM it is also necessary install the BASIC ROM in the slot 0.


If the flash memory is corrupted and you can't start the system with the Megaflash plugged in, then you can change the switch in the bottom back of the interface to disable the interface during the start up.
Then return the switch to the original position and load ROMAN from the disk to erase all and populate again.

[Audronic]

Hi Wilco2009

I have tried all of the above.
I have had no success programming the MegaFlash on my CPC6128.

I have Read the Rom from the other unit i purchased from you in an Eprom Programmer (TOP853)
and dumped it in the Rom of the first one (edge Connector)

The Megaflash Plus SX now is able to boot , read the Roms etc.

BUT if i try and WRITE to the Rom it performs all the actions on screen OK but does not WRITE to the ROM successfully.

I have had a look at a Dump of a Rom that i tried to write to and it puts some garbage into the Rom (Checksum Changed).

The model i am using is the EDGE connector version.
I have tried to do .
1) Unprotect the Rom.
2) Initialise the Rom.
3) Erase all 32 Roms.

None of that works ??

What can i do to get this to Write to the Rom ??

Ray

[wilco2009]

Hi Wilco2009

I have tried all of the above.
I have had no success programming the MegaFlash on my CPC6128.

I have Read the Rom from the other unit i purchased from you in an Eprom Programmer (TOP853)
and dumped it in the Rom of the first one (edge Connector)

The Megaflash Plus SX now is able to boot , read the Roms etc.

BUT if i try and WRITE to the Rom it performs all the actions on screen OK but does not WRITE to the ROM successfully.

I have had a look at a Dump of a Rom that i tried to write to and it puts some garbage into the Rom (Checksum Changed).

The model i am using is the EDGE connector version.
I have tried to do .
1) Unprotect the Rom.
2) Initialise the Rom.
3) Erase all 32 Roms.

None of that works ??

What can i do to get this to Write to the Rom ??

Ray

When the chip is dumped with an EPROM programmer it left the chip write protected.
The esasiest way to unprotect the chip is to use the unprotect function in the programmer.


It must be possible to unprotect it from ROMAN, but if you are still having problems I'll check it in my interface when I will return to home next week.

[00WReX]

Hi Audronic,

I had some issues last year with a Megaflash and not being able to write to it from the CPC.

Anyway, check this out from almost a year ago (I have just done a couple of all dayers / all nighters at work with some major issues so I'm running on minimal sleep and this may not be 100% relevant, but from initial quick read it sorta sounds similar...maybe...).

MegaFlash issue

Cheers,
Shane

[Audronic]

Thanks Shane


I will have a Look




Ray

[TFM]

I have had no success programming the MegaFlash on my CPC6128.

Hi, if roman doesn't work then you can try to use my ROManager 2.14 (Link: ht tp://futureos.cpc-live.com/files/ROManager_ALL.zip). Why?

It will check every operation, does protect / unprotect etc. automatically. And the main screen will immediately show you if there is a problem or not.

However, you would have to install FutureOS to run it. Further I never used it for Wilcos expansion in person, but I had some guys doing test for me and so I think that's the best alternative for you. Let me know if I can help in any way.