Arnold with MOS 6502

[Hammer]

I recently read that the cpc prototype called "Arnold" was planned to be build around a MOS 6502 cpu. But what were the specific reasons to finally move to the Zilog Z80? In fact wouldn't that mean a lot of (costly) changes in the architecture and therefore quitting a working prototype?

[eto]

But what were the specific reasons to finally move to the Zilog Z80?

Timing. They needed BASIC and firmware. They discussed with Locomotive which said "we can develop the firmware and BASIC with that deadline but only if you build a Z80 based machine". Sticking to the 6502 would have meant to use something like Microsoft BASIC or release the CPC a lot later. But it was not such a big deal as ...

changes in the architecture and therefore quitting a working prototype?

... they did not yet have anything working at that point.

There are plenty of interviews with Roland Perry in the last 2-3 years where he goes into details. I don't have a link right now but if you google for interviews with him or check Youtube you should find it.

[dodogildo]

I recently read that the cpc prototype called "Arnold" was planned to be build around a MOS 6502 cpu. But what were the specific reasons to finally move to the Zilog Z80? In fact wouldn't that mean a lot of (costly) changes in the architecture and therefore quitting a working prototype?

This has been well discussed before: https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/the-cpc-revision-zero-article/

[andycadley]

Although they didn't really have a working prototype (and by all accounts were unlikely to get one), I think you can still see aspects of the 6502 heritage in the CPC.

The arrangement of having the gate array refresh RAM (rather than just use the built in Z80 refresh) and the way the gate array uses the memory bus tend to align with how you'd do things with a 6502, so it's probable that they avoided changing any designs they did have as much as possible anyway.

[eto]

The arrangement of having the gate array refresh RAM (rather than just use the built in Z80 refresh)

If you would use the Z80 refresh it would not be possible for the GateArray to read screen RAM during M1 CPU cycle. The requirement/idea to interleave access to Screen RAM and CPU RAM would probably have led to that decision even if they would have started with the Z80 from the beginning. (Side question: do any of the other Z80 based homecomputers, which do not have their own screen RAM, use the R register for RAM refresh? )

[robcfg]

Remember we have nice pictures of the 6502 prototype here: https://www.cpcwiki.eu/index.php/Mainboard_Versions#CPC464_version_0_Prototype 

[andycadley]

(Side question: do any of the other Z80 based homecomputers, which do not have their own screen RAM, use the R register for RAM refresh? )

The Spectrum does, as do it's younger brethren the ZX81 and ZX80 I believe. I still suspect the requirement to interleave memory access the way it does is a bit of a 6502ism (the 6502 only ever accesses the bus on alternate cycles precisely to allow video circuitry or other peripherals unimpeded access). A system designed around the Z80 and it's refresh mechanism would've likely just worked differently from the start.

[Bread80]

One of the key features affecting the Amstrad's memory accesses is the size of the video RAM. Reading 16kB per half-frame requires reading two bytes per gate array cycle and leaves very little time for anything else. If they had chosen to use the Z80's refresh they would have had to interleave between refresh and CPU access on alternate gate array cycles with an effective CPU speed of only around 2MHz. Using the CRTC to double as refresh is part of the cleverness of a design which wouldn't have worked without it.