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General Category => Technical support - Hardware related => Topic started by: Wawavoun on 13:26, 29 May 23

Title: CPC6128 Gate Array READY signal
Post by: Wawavoun on 13:26, 29 May 23
Hello,

I am working to an expansion board for my CPC 6128 and have some questions about the 'READY' signal (not the one from the floppy).

This signal is drive by the gate array (pin 22) via a 82 ohms resistor.
Is goes then to the Z80 (/WAIT pin 24, enable processor halt), to the LS373 for the data latching on the data bus during the wait and to the expansion connector. So obviously its an output !

Nevertheless I see numerous schematics where this line is (at some time) pulled low by the expansion board so the processor wait sometime for something.
This give a 61 mA current on pin 22 of the gate array if he try to keep this line high during the same time...

I am asking myself if this situation is 'normal' and if it is possible to keep this line low without more check ?
Or if may be the gate array internal design is made so that he never try to give this line high when the Z80 is in wait state ?

More generally how to manage this signal if we want that the processor stay waiting for example during a floating point unit operation.
The fpu give a signal /PAUSE saying when high 'I am ok for a new command' or saying when low 'I am still busy'.

Thanks and regards.
Philippe
Title: Re: CPC6128 Gate Array READY signal
Post by: IanS on 13:44, 29 May 23
The signal is shown on the 464 schematic as an Open Collector output, so the Gate Array is only actively pulling it low. I pressume it's the same on the 6128. Multiple devices can pull it low without harm.
Title: Re: CPC6128 Gate Array READY signal
Post by: Wawavoun on 14:25, 29 May 23
No mention of open collector and pull up resistor on CPC6128 schematic...



Capture.JPG



But could be yes ?
Title: Re: CPC6128 Gate Array READY signal
Post by: gerald on 16:56, 29 May 23
On the 40007, according to the schematic,  the output is an open collertor with a internal 600 ohm pull-up.
The 40010 uses a full CMOS buffer. To keep the wired AND functionality, there is a 82Ohm resistor at the 40010 output so you can pull it low with an external device.

The Ready signal is periodic and is low 75% of the time (12 16MHz cycles every 16), so pulling it low will only "short" it for 25%, so an average 15mA.

Note : the ready is only an output. The GA does not care about it.
Title: Re: CPC6128 Gate Array READY signal
Post by: Wawavoun on 20:21, 30 May 23
Very clear !

Thank you.

Philippe
Title: Re: CPC6128 Gate Array READY signal
Post by: Animalgril987 on 23:45, 30 May 23
@Wawavoun you are making a maths co-processor, for a CPC?
Cool!
Title: Re: CPC6128 Gate Array READY signal
Post by: Wawavoun on 07:38, 31 May 23
Hi,

I try yes !

Its my first experience of diy for CPC/Z80 so I am in the hard with the address decoding.
See here : https://www.cpcwiki.eu/forum/hardware-related/cpc6128-expansion-board-address-decoding/25/

Hope I will find an explanation of what I see ?
 
Regards.
Philippe
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