According to 765 FDC - CPCWiki (http://www.cpcwiki.eu/index.php/765_FDC) there are a set of status bytes returned by the FDC but I don't understand the values I'm getting following a read operation.
This is being done on a Philips P2000C which is a CP/M machine that uses the same FDC as the good old CPC. The drive is accessed via a diagnostic tool in the BIOS and it appears to be showing the status bytes after each operation.
When reading a track (track zero, side zero, drive zero) from a floppy I am getting:[/size]40 01 00 00 00 01 01According to the service manual these are the uPD765 floppy controller's RESULT bytes (it should show OK if the operation was successful), but I don't know how to interpret them.
I looked at the datasheet for the controller and it mentions the main register and four others, but only gives the meaning of the four registers. I am not sure if one of these is the "RESULT" byte, or if it is the status register.When attempting to write to the floppy, I also get 40 01 00 00 00 01 01.
When attempting to write to a write protected floppy, I get 44 02 00 00 00 01 01.I do not know how to interpret these results, can anyone help?
Another question: Generally if the disk is corrupt or unformatted would this sort of low level access work or not? I mean, the format is at OS level, but I am making direct calls to the BIOS to write / read a track. would this be expected to work on a corrupted disk?
Thanks
jonB
Don't confuse FDC registers and bytes delivered during result phase.
getting &40 as first result byte is ok
Get some serious FDC765 docs! :)
I've tried to read the data sheet but it is not clear on how you interpret the result bytes - hence the question...
Can you tell me what they mean, or point me to a doc that does?
Cheers
JonB
PS, 40, nice one - that is a step in the right direction.
JonB do you know this doc.?
http://www.google.pl/url?sa=t&rct=j&q=&esrc=s&source=web&cd=4&cad=rja&uact=8&ved=0CDwQFjAD&url=http%3A%2F%2Fwww.classiccmp.org%2Fdunfield%2Fr%2F765.pdf&ei=iJkhVfq9IYWUsAHX_YOwBw&usg=AFQjCNHshd8Lh5TD51DK-WjQ-_dCJJ4BBg&bvm=bv.89947451 (http://www.google.pl/url?sa=t&rct=j&q=&esrc=s&source=web&cd=4&cad=rja&uact=8&ved=0CDwQFjAD&url=http%3A%2F%2Fwww.classiccmp.org%2Fdunfield%2Fr%2F765.pdf&ei=iJkhVfq9IYWUsAHX_YOwBw&usg=AFQjCNHshd8Lh5TD51DK-WjQ-_dCJJ4BBg&bvm=bv.89947451),d.bGg
It is interesting, because it contains not tables only, but also functional description of commands.
Hi Jon,
Each command *can* return different status bytes.
For example, a sense drive status returns st3. In this case the status register is specific to the drive you did the sense drive status command on.
For sense drive status each bit has a meaning. 1 means true, 0 means false.
so bit 6 - write protect - is set if the disc in the drive is write protected. Here write protected means the write protect tab on the physical disc itself; which is ultimately read by a sensor and reported by the drive.
it will be 0, if the disc in the drive is set to read/write.
Looking at a read data command.
The first three bytes are ST0, ST1 and ST2. The next 4 bytes are C,H,R,N at the point the command was completed.
The NEC likes to be driven in the following ways:
1. DMA controlled. DMA controller does all the work and all the appropiate acknowledgement and indicating to the FDC when it's finished reading and to terminate the command.
2. Interrupt driven. IRQs are asserted on the host CPU, these are used to read data from the sector and to know when the command has completed.
It also likes the TC/Terminal Count input to be asserted, this tells it we have finished reading sectors.
The interrupt code, represented by bits 7,6 therefore will report success or not - but it's not as simple as both bits being 0.
On the CPC, polling method is used. Neither interrupts or DMA are used and TC is not connected. This means FDC will often give an "abnormal termination" because it didn't receive TC input. But, it's actually ok in this case, the complete sector has been read/written and the appropiate results are valid.
Bit 5 of ST0 is only valid when a seek command has been sent to FDC. It is best read using sense interrupt status and will tell you when the head has finished moving to the requested track - be aware if you're moving more than 77 tracks you will see bit 4 set and you will need to repeat the seek a second time. It's in the docs.
Bit 3 indicates that when the command was executed by the FDC the read state of the drive changed. It went from not-ready to ready (e.g. a disc is now in the drive and the motor has spun up) or ready->not ready (disc motor was turned off, or disc removed from drive).
bit 2,1,0 are like a status. They are more important with sense interrupt status. The fdc checks 4 drives and if the ready state changes, it will tell you which changed through these bits. Otherwise they are generally the bits you set for the side and drive in the command.
ST1 - Bit 5 - Data Error - this means there was an error reading the sector, the data checksum for the ID part (which holds the C,H,R,N values for a sector) and/or the checksum for the data part were bad.
Think of data on the disc like this:
<id field containing C,H,R,N matched with values in command> <gap> <data field> <gap> <id field for next sector> <gap> <data field for next sector>
ST1 - Bit 4 - Overrun - This will be set if you don't read the data or write the data from the sector fast enough. The FDC expects data at a fixed rate and if you're too slow it will indicate to you and fail the command.
ST1 - Bit 3 - No data - Set if the FDC can't find any valid ID fields or the c,h,r,n you sent in your command doesn't match any of the C,H,R,N stored in the id fields on the disc.
ST1 - Bit 2 - Not writeable - set if you do a write sector and the disc is write protected.
ST1 - Bit 0 - Missing address mark - this means FDC failed to find any valid ID fields on the disc, it tried for 2 rotations but nothing.
ST1 - Bit 7 - I can't remember the conditions for this, I think if you set the read command to read multiple sectors and it fails to find 1 it will fail with this error. Can't remember.
ST2 - Bit 6 - If you used READ DATA command, but the sector had a "deleted data" mark. This will be set. OR you used READ DELETED DATA command, but the sector had a "data" mark. The "deleted data" is just a byte, it doesn't mean the data has been deleted.
ST2 - Bit 5- When reading the data for a sector the fdc found an error. checksum didn't match data.
ST2 - bit 4 - FDC found a sector with matching R value, but the C value didn't match the one you passed in the command.
ST1 - bit 1 - similar to bit 4, but where C was ff. I think C in the command. Can't remember exact details.
ST2 - bit 0 - FDC found a matching ID field, but didn't find a data field. Remember id field and data field are stored seperarely.
I hope that helps?
Right... Using 22DISK with a specific set of drive parameters allows me to read the P2000C disks and they all appear to have CPM on them.
I'm using the "read track" test in the BIOS and getting the result bytes 40 01 00 00 00 01 01 (http://www.cpcwiki.eu/forum/tel:40%2001%2000%2000%2000%2001%2001).
On revisiting the u765FDC datasheet it looks like they are interpreted as follows:
40 is Status Register 0. A binary value of 01000000 (http://www.cpcwiki.eu/forum/tel:01000000) - D7 clear, D6 set; which means "Abnormal Termination of Command (AT)".
01 is Status Register 1. A binary value of 00000001 (http://www.cpcwiki.eu/forum/tel:00000001) - D0 set; which means "Missing address Mark (MA)".
These agree with what you wrote, arnoldemu (very nice description, by the way - might be good to add it to the wiki page on the FDC). I get this result set consistently on any disk which, in the PC, I can actually read the directory from, and I can even see what the (text) files contain. So I guess the question is: Why am I getting a missing address mark every time I try to read a disk on the P2000C? Could I have a faulty connection or FDC?
I think the drives themselves are OK, as I am using one on the PC to read the disks.
JonB, what kind of this P2000C disks you have - single or double sided?
Let's say...:
If your "read track" command has D7 bit set to "1", which means Multi Track Mode operation
(manual: Multi Track Mode - after finishing Read/Write operation on side 0, FDC will automatically start searching for sector 1 on side 1)
and your disk is one sided, so after successfull read of side 0 track, FDC switches to side 1 and trying to find Address Mark on next track. Of course this AM does not exists on SD Disk, and command terminates with "1" in D0 of Status Register 1 - Missing Address Mark.
I would say don't use read track.
If you can use multiple "read id"s first. You will see a pattern and where it repeats you can find the number of sectors on the track and their ids and sizes. Take the last 4 bytes of the status to get each of the CHRN.
On CPC they look a bit like this for track 0:
0 0 C1 2
0 0 C2 2
0 0 C3 2
0 0 C4 2
0 0 C5 2
0 0 C6 2
0 0 C7 2
0 0 C8 2
0 0 C9 2
Then use read sector on just one of those specifying the C,H,R,N values in your read data command. e.g.
0 0 0 C1 2 C1 2A FF
On CPC the read data report looks a bit like this (from memory).
40 80 00 00 00 C1 02
Read track is a bit more tough to use because it's working from the start of the track and it's doing a special comparison with the id values.
Quote from: kevin.c on 08:29, 07 April 15
JonB, what kind of this P2000C disks you have - single or double sided?
Let's say...:
If your "read track" command has D7 bit set to "1", which means Multi Track Mode operation
(manual: Multi Track Mode - after finishing Read/Write operation on side 0, FDC will automatically start searching for sector 1 on side 1)
and your disk is one sided, so after successfull read of side 0 track, FDC switches to side 1 and trying to find Address Mark on next track. Of course this AM does not exists on SD Disk, and command terminates with "1" in D0 of Status Register 1 - Missing Address Mark.
I would follow Kevin's advice here.
Use a single read data command, not multi track and turn on MFM mode. I assume the discs are double density recording - could be wrong though. Set side and drive to be 0 and 0.
Input the CHRN as I mentioned before and you should get nicer looking values AND if it works, you should have either overrun or a buffer of data :)
In my previous post I wrote: "(...) AM does not exists on SD Disk" . Of course I meant Single Side disk, not a Single Density one... Sorry for my mistake.
Well, if you really read the sector id's on a Data Disc it look like this
C1, C6, C2, C7, C3, C8, C4, C9, C5.
Because the tracks get formatted with an interleave of 1.
I only have access to read a track in the P2000C's monitor. The command is documented in the attached image below. The disks are DS DD 80 track and as you can see, I can select a track from a specific side of the disk, but nothing else, no sector addressing, for example.
The only way to test other functions of the FDC would be to write some machine code then enter it into the monitor one byte at a time (using a separate "set memory" command for each byte, rather painful!
Now the FDC uses a PLL to detect address marks, and it has a reference frequency of 500KhZ. But I measure mine at 303kHz and the adjuster has no effect on it. I'm wondering if there is a component in the PLL circuit that's failed, but I know zero about them. The PCB certainly has quite a few discrete components around the trimmer, including some electrolytics. Maybe if I recap it..?
PLL for reference. TP2 is at 303Khz.
Can you post a circuit diagram of the fdc from the p2000c?
it should be possible to determine what parts of the nec765 document apply.
Pin 8 of the 74LS293 top right is @ 150Khz, should be 250. Pin 10 is @ 500Khz, correct.
So should I conclude the '293 is bad?
No. The 293 is receiving the 250khz, not producing it, so it's probably ok. What part creates the 250khz?
Sorry, correction. The 250khz should be coming out of the 293, why do they show the arrow in the wrong direction?? Anyway, yes, this could mean that the 293 is faulty.
Bryce.
I have one lying around somewhere. :D
Here is the controller circuit diagram.
Ok, I went to the bother of actually checking the datasheet (which I should have done in the first place) :D What frequency do you measure on pin 11 of the 293? What are you using to measure the frequency?
It looks like the 293 is probably ok, the input clock is probably wrong though.
Bryce.
This circuit is clock recovery from Read Data, and correct output frequency on pin8 depends on
1.presence of correct data read from diskette
2. correct revolution rate of floppy
I'm sure that on standby - I mean floppy is stopped - the output clock frequency will be random, and that is the case.
Ah, you're right, I didn't look at the whole circuit (extremely difficult on a phone), just the 293. I thought this was just a clock generator for writing.
Bryce.
Write data circiut is very simple, it just require divided cristal clock. This PLL is to compensate read data clock jitter.
Frequency measurement will be valid on stable data read out. In other case PLL is out of synch.
I'll take a proper look at the schematics when I'm home and at my computer. Scrolling around a 4in screen is a pain.
Bryce.
Hi Bryce
I have a frequency counting multimeter here, it's accurate enough.
Turns out I don't have a 293 lying around, drat and double drat!
The measurements are:-
pin 4 - 302.5khz
Pin 8 - 151.2khz
Pin 9 - 250khz
Pin 10 - 500khz
Pin 11 - 1200khz
Is this consistent with a fully functional '293?
Pin 4 is supposed to read 500khz as it is connected to the test point.
It also says you should ground pin 3 (CLR) of the chip labelled 7415 (74LS221) before taking measurements (and making adjustments), but this doesn't alter the readings. Would this be to force it into a stable state?
JonB why we came to PLLs and counters, instead of secret FDC bits ;D ;D ? Anyway I find it interesting...
(Serious hat on.. I realise you're joking) ...Because the FDC is using the PLL to detect the address mark on the disk, or rather, to interpret the read data bit. Err, I think. Either way, on this machine the designated test point for the PLL is showing the wrong frequency, and the PLL is all tied up with the read pulse. We have deciphered the error which is "missing address mark" and so I am looking into how the mark is read. I know the disks are OK because I can read them on a PC with 22DISK (a nice bit of software for transferring files to/from a gazillion different co/m formatted disks, including the ones used by the P2000C).
So the missing address mark isn't caused by the disks, or the drives (already independently tested with the P2000C disks and 22DISK). Therefore there is something wrong with the circuit that controls the read. The FDC is starting up fine. I can see this because the seek occurs, as does spinning up the drive and stopping it as well as head load and unload; it all looks normal. All that is left (that I can think of, anyway) is the actual read signal.
Hence, we are now debugging the PLL... Your advice is very much appreciated! :)
Just a question: Have you tried formatting a new disk in this setup and reading it back?
Bryce.
from the diagram I can see:
support for 4 drives
double sided supported
uses terminal count input; so this needs to be asserted correctly to stop the abnormal termination of command (assuming it's not a genuine error)
looks like it's double density only
missing address mark can also come if it's attempting to read a double density disc when set to single density and reading a single density disc when set to double density.
Can you confirm the clock to the fdc is correct?
Another question: It seems you have a broken p2000c which will not boot and you are fixing it?
@Bryce (http://www.cpcwiki.eu/forum/index.php?action=profile;u=225): can't use the machine to format a disk because it won't boot at all. However I do have some disks that were supplied with it and are readable on a PC with special software (22DISK); they look like CP/M boot disks.
@arnoldemu (http://www.cpcwiki.eu/forum/index.php?action=profile;u=122): yep, it's a P2000C that won't boot. Also has a problem with its terminal board, but that is a separate issue, you can connect a PC via RS232 to the mainboard and forget the terminal board altogether (which is what I have done; I'll fix the terminal board once the thing is booting into CP/M).
It has an inbuilt ROM based monitor / diagnostic tool called IPL that allows you to read and write tracks to a disk without booting. It is this command (read track) that is failing with missing address mark, but write track also fails. I think I t can read lower density disks; I assume this because some software was supplied on 160k floppys (assumed SS/SD) and there is a CP/M utility that you use to transfer to 640k disk.
As previously mentioned, the service manual says we should get 500khz at TP2 when the CLR line (74LS221 pin 3) is grounded. As I do not get this (it's reading 303khz), and I can't get the adjuster (trimmer labelled 4712) to alter it, I think the circuit is broken.
I will check the circuit as requested later on (when I get home).
Thanks
JonB
Oh, a thought. Is it possible some discrete component has failed like a capacitor? Some of them are electrolytic.
Well I've had a chance to look at the schematics and the datasheets now. The 293 seems to be working normally. Pin 4 should be dividing the signal on pin 11 by 4 which it's doing: 1200/4 = 300. So to get 500 on TP2 you'd need 2Mhz on pin 11 which you don't have. So now the question is - Why not?
MC4024 is a voltage controlled multivibrator. It's being used in the voltage controlled mode, so Pin 2 (Vin) decides the frequency that it outputs. First off check the other pins to make sure it's getting what it needs:
Pin1 and 14 should be at 5V
Pin 5, 7 and 9 should be to GND
All good?
According to the datasheet, the MC4024 can output from 1Mhz to 5Mhz by varying the voltage to pin 2 between 2.5V and 5V. So to get 2Mhz pin 2 would need to be at about 3.25V. Is it? If not it's time to go back a step further and take a look at the 741 circuitry.
Bryce.
Bryce, I have this so far (measurements already taken round the 741)
+12 and -12 volts are present. The output voltage is .6v (at Pin 6).
So if it needs to be higher, we might conclude that some stuff round the 741 is damaged. The 741 inputs are both at 400mv wrt ground.
If you can give me a list of test points, I can take measurements in one go. Unfortunately I have a tiny amount of time in the evening to do this, so it's better to try and do as much as possible in each session. My train is already 45 mins late tonight so that cuts down my evening time even more. :(
And I am really keen to fix this machine. It's so frustrating....
Quote from: Bryce on 13:41, 08 April 15
.......... So to get 2Mhz pin 2 would need to be at about 3.25V. Is it?..........
Bryce.
Bryce , this above is valid under condition that PLL loop is closed: to pin 30 RDD is applied stable Data Read signal, or if control line "SYNC pin24" is set to "0", then to PLL is applied reference 250kHz from pin 9 of 293 counter. In this case PLL is synchronised and stable. IMHO it is for faster synchronisation in case switching PLL to RDD signal.
Just remember we are grounding the CLR on the left hand 221 before measuring frequency. I think this is intended to lock it down (so it won't depend on the disk signals). Have I got that right?
Quote from: kevin.c on 19:55, 08 April 15
Bryce , this above is valid under condition that PLL loop is closed: to pin 30 RDD is applied stable Data Read signal, or if control line "SYNC pin24" is set to "0", then to PLL is applied reference 250kHz from pin 9 of 293 counter. In this case PLL is synchronised and stable. IMHO it is for faster synchronisation in case switching PLL to RDD signal.
According to the service manual, this is also valid if he grounds pin 3 of the 221. So without any disk spinning or data reading he should be able to do all these tests.
Bryce.
I see Bryce... It looks that clearing this pin 3, the phase comparator is reset to "0".
JonB check following please :
1. ground pin 3 of left 221 as before
2. check if pins 5 and 9 of LS112 are both in "0"state
3. measure voltage on pin 6 (output) of 741, turn gently current source regulator R4712 and observe voltage change on 741 output.
For any case mark regulator 4712 factory position...
Good check, but I've a feeling the voltage won't change much, if at all. My bet is on a failed Zener at the moment.
Check the Zener output voltages while you are at it.
Bryce.
Grounding Pin 3 of 221
Pin 5 0 state with pulses about every 500ms
Pin 9 0 state with pulses about every 500ms
Does not make sense but anyway...
Pin 6 of the 741 is at -300 mV and adjusting the pot makes about 30mV difference either way.
That said I am having difficulty holding the wire onto 222/P3 and trying to make measurements. I will need to solder a strap to GND in place, because I don't have any of those little clip things.
Please see attached image. Might it be this (highlighted) bit that's not working? Feels like I'm fumbling in the dark at the moment.
Check the voltage on zener diode as Bryce said.
Quote from: Bryce on 21:48, 08 April 15
Good check, but I've a feeling the voltage won't change much, if at all. My bet is on a failed Zener at the moment.
Check the Zener output voltages while you are at it.
Bryce.
Don't get you. The voltages before or after the zeners? You mean 7505 / 7503?
Zener: -> points to black band (output?), measurements at both sides:
7503 0v -> 5.5v
7505 -12.15v -> -12.15v
To simplify electronics jargon... :D
Voltage measured on Zener diode 7505, as shown on schematic, should be always 5,6V (tolerance 0,1-0,2 V)
http://www.nxp.com/documents/data_sheet/BZX79.pdf (http://www.nxp.com/documents/data_sheet/BZX79.pdf)
That's a voltage regulator. The input and output voltages are the same (measuring wrt GND) so without actually measuring across it as you show in your annotation, I'd say it will measure at 0v. But I'll check it when I get home tonight.
Quote from: JonB on 07:04, 09 April 15
....The input and output voltages are the same ....
This means you found the fault! The Zener diode (=voltage regulator) is broken down. (short circuit). I hope there is no more faulty elements because of short circuit. As you can see on schematic, -12V came directly to resistor 3314.
By the way... Bryce bet on good horse. ;D
:) Looks like my suspicions were right. Unfortunately, this might also mean that further parts have been damaged (looking at you BC549 - 7302 not 7303).
Bryce.
OK, I should have 2 C5v6 Zener diodes and 2 BC549s by the weekend. I'll swap out the first Zener and recheck.
Is there a way to test the ctransistor or should I just swap it out anyway? I'm reluctant to do it because both transistors are bound tightly together by a rubber tube (why?) so will be tricky to take out.
Quote from: JonB on 11:48, 09 April 15
OK, I should have 2 C5v6 Zener diodes and 2 BC549s by the weekend. I'll swap out the first Zener and recheck.
Is there a way to test the ctransistor or should I just swap it out anyway? I'm reluctant to do it because both transistors are bound tightly together by a rubber tube (why?) so will be tricky to take out.
Binding the two resistors is to ensure that they both experience the same thermal drift (gain change due to temperature). This is often done on voltage reference circuits when one Transistor is going to have a higher load than the other. By binding them together they share the same temperature and hence the same amount of drift.
Bryce.
Hmm thought as much. So I will need to bind them somehow after replacement. Hopefully I can slide the sleeve off without damaging it.
For the begining replace the faulty diode only. First measurement of 741 output voltage will answer if transistors are ok.
I was going to ask about that. Turns out Maplins had no transistors in stock so I only have the Zener. Do you think it is likely the replacement diode will blow if the transistor is dead?
Anyway, I'm going to do it. First bit of repair work on the P2000C - it's been diagnostic up till now.
So the P2000C has two Z80 CPU's right? At which speed to they run? Is it 2.5 MHz?
It's hard to get docs about that nice piece of hardware :)
Supposed to be one of the best CP/M machines there is.
Twin CPUs, both 4Mhz. One for I/O, one for general CPU tasks. 64K RAM, has DMA for disk transfers. 3 second cold boot, if YouTube is to be believed. Also has built in interfaces: SASI HDD , serial, parallel and external floppy plus external monitor connector in case you don't fancy squinting at the dinky 9" screen. Supports high rez graphics (monochrome). Twin 640k 5.25 floppies (Teac FD55); modern, low profile keyboard. Has MSDOS capability if optional 8088 board is fitted (not present in mine, unfortunately). There are other boards that could be fitted to the one slot, but they are rarer than hen's teeth.
Oh and it's "portable" too, ha ha!
Yet another computer museum - P2000C (http://electrickery.xs4all.nl/comp/p2000c/)
All docs & disk images at the above link, including (crucially) the service manual. Mine has all user documentation plus some extra software on disk.
Super fast boot video : Fastest booting PC in the world (3 seconds to commandprompt) (http://www.youtube.com/watch?v=8FCw6mJH5VE#)
Now you can see why I want to repair it so much. It's pretty, compact, capable and totally kicks CP/M ass.
Drat, foiled again. Maplin had the transistors but not the Zener diodes (their web site lied). So now I have to wait "3-5 working days" before I can progress.
Very nice machine indeed. :) My Genie IIIs is not bad either.
Replace the diode first. Even if the transistors are damaged, they won't damage the new diode. As far as binding the new transistors (should you need to replace them). You just need them to be pushed tightly together, so any method will do. I usually glue the faces (flat sides) together and then put a cable tie around them.
Bryce.
Quote from: TFM on 20:04, 09 April 15
Very nice machine indeed. :) My Genie IIIs is not bad either.
One of these?
http://www.old-computers.com/museum/computer.asp?c=130 (http://www.old-computers.com/museum/computer.asp?c=130)
No, it's from TCS. Runs CP/M 2.2 and Plus, NewDOS 80, G-DOS and such stuff. Has two Z80 CPU's both with 8 MHz, first has 256 KB RAM, second hat 64 KB RAM. Memories can be mixed. Textmode and GFX mode (hires, 64 KB V-RAM), CRTC 6845 like CPC, but differently connected.
Two 5.25 drives, also two external two 8" drives with 1.8 MB format.
Has two SIO and two PIO.
Was used as computer for a hospital before.
RTC and slots for expansion cards.
Didn't ever get the HD for it :(
Green monitor, but plug to external monitor too. Only sound is a bit weak.
It's FDC is not as easy to use as the FDC765, but can do lot's of things.
A bit like this, but better ;-)
http://www.homecomputermuseum.de/comp/188_de.htm
8Mhz? OMG... :o
TCS Genie IIIs, derived from our old pal the Video Genie. But what a machine. Must be real fast..!
Probably the 3rd quickest. (Dunno if it would be doable to add more Z80 cards with own 64 KB RAM though).
2nd quickest is the RT280 with 12.5 MHz Z280 CPU from Tilman Reh
1st quickest is a self made computer from Dr.Zed with 25 MHz (was it Z80 or Z280, I don't remember).
It was Z280
About VIDEO GENIE III: I like this - "external 5 MB hard-disk"! My youngster doesn't belive me. For him poor HDs start with 250GB!
That's a coincidence... I'm about to make a 25mhz z80 thing using a FPGA.
...thanks to Grant Searle, that is : Grant's MULTICOMP pick and mix computer (http://searle.hostei.com/grant/Multicomp/index.html)
..and..
Grant's home-designed CP/M machine (http://searle.hostei.com/grant/Multicomp/cpm/fpgaCPM.html)
Total cost, about £30.
Quote from: kevin.c on 19:46, 10 April 15
About VIDEO GENIE III: I like this - "external 5 MB hard-disk"! My youngster doesn't belive me. For him poor HDs start with 250GB!
The IIIs had 10 MB (wohooo!), But my Dobbertin at the CPC has 20 MB, still only 1/3 full. What to do with so much space? :laugh:
OK, I have changed the Zener diode 7505 on the PLL schematic and was able to set the 500Mhz test point correctly. I checked the points at top right (250kHz / 500kHz) and they are both correct. Pin 11 of 7433 (connects to the output - pin 6 - of the VCO) is at 2Mhz.
I am now getting a different result:-
C0 00 00 00 10 00 FF
..which seems to be
C0 : abnormal termination because disk ready signal changed state (D6 / D7 = 1)
00 : ST1 - nothing
00 : ST2 - nothing
00 : ?
10 : ?
00 : ?
FF : ?
I am tracing the logic circuits back with a probe. (in the following the component number is given with the pin in brackets immediately after).
The sync pulse is there 7415(2) B1 and 7415(10) B2.
Q1 Output of 7415(13) is pulsing.
Q2 output 7415(5) is the RD signal, pulsing.
7415(11) - CLR2 is high.
7415(3) - CLR1 is high.
!Q1 7415 (also TP1 where you are supposed to get a 1uSec pulse) is pulsing but I can't measure it without a scope.
Q1 7416(5) is pulsing.
Q2 7416(9) is LOW.
J2 7146(11) is pulsing.
K2 7416(12) is pulsing.
7416(13) is HIGH.
7416(2) is HIGH.
7416(1) is pulsing, at 500kHz as expected.
So the only thing I can see at the moment that might be wrong is the Q2 output 7416(9) which is stuck low, but feeds the non inverting input of the 741 op amp. But the op amp is working now, and we can see the output voltage changing in the correct range and setting the VCO to give 2Mhz output at its pin 6 (and thus, to 7433 and out to 7433(4) where the 500kHz test point is showing the correct frequency (as previously stated).
The only other adjustment is the 1uSec test point which cannot be tested without a scope.
Congratulations. Looks like the hardware is getting closer to doing what it should.
Bryce.
Thanks Bryce, and a good call on the Zener diode!
..but I'm not out of the woods yet.
I should say that in order to get the TP2 to 500kHz it was necessary to set the potentiometer 4712 and I can see that it is slightly off the factory setting (black gunk now misaligned). So perhaps the 1uSec adjustment has drifted (pot @ 4713). Shame I have no scope... :( :( but I bet there will be something else wrong even after adjusting that. It really is that poorly.
Anyway, while you were replying I updated my previous post with various measurements from the circuit... What might I check next?
Buy yourself one of those cheap shit frequency counter kits: DIY Kits 1Hz-50MHz Crystal Oscillator Frequency Counter Meter Digital LED | eBay (http://www.ebay.co.uk/itm/DIY-Kits-1Hz-50MHz-Crystal-Oscillator-Frequency-Counter-Meter-Digital-LED-/111614247462?pt=LH_DefaultDomain_3&hash=item19fcba4226)
It's a fun little project and is good enough to adjust the frequency accurately. I'd clean the pot first, because all the gunk it gathered over the years is making the resistance very variable.
Or if you're lazy there's a fully built version with LCD: High Accuracy RF 1 to 500 MHz Frequency Counter Tester measurement For ham Radio (http://www.ebay.co.uk/itm/High-Accuracy-RF-1-to-500-MHz-Frequency-Counter-Tester-measurement-For-ham-Radio-/111614252504?pt=LH_DefaultDomain_3&hash=item19fcba55d8)
Bryce.
I have a frequency counter already - one of these:
Uni-Trend UT60E RMS Autoranging Digital Multimeter with PC Interface | Maplin (http://www.maplin.co.uk/p/uni-trend-ut60e-rms-autoranging-digital-multimeter-with-pc-interface-n81cb)
It is showing a steady 500kHz at TP2. Do you think I should measure the frequencies at the various test points mentioned in my last post? Those were just to check a signal was propagating through the logic ICs (used this approach to diagnose a faulty PET).
Then you should have no problem calibrating everything. Yes, rule No. 1 - measure and verify every voltage and known value that you can.
Bryce.
I can't calibrate the 1uSec pulse at TP1 without a scope, unless there is a way to use the meter's frequency counter or hold function. Hmm. Have to look into that. The calibration says you are looking for a 1usec pulse width (between the rising and falling edges of the pulse). I don't suppose I can use the multimeter for this...
As to the other measurements, the only known values are at the two test points and the others as marked on the circuit diagram. So I can do frequency measurements at the points I already measured for logic pulses, but I'm not sure what the expected results should be.
Any idea? I suppose for the dividers I can calculate.
1µs = 1Mhz. If it's a constant signal you should be able to measure this with the Uni-T. If they are single pulses, then you'll need a scope or at least a counter. Pity that Uni-T didn't include a counter, it would only need some extra firmware.
The normal first measurements when fixing something is:
- Check the input voltage and current - Confirm both are what would be expected.
- Check supply voltage on all ICs (That they are within the specified operation voltage stated in the Datasheet).
- Check any reference points (voltage, frequency, waveform) given in the service documentation.
Bryce.
Well, I have ordered one of these so I should be able to resume the search in due course.
http://www.rigol-uk.co.uk/Rigol-DS1054Z-Digital-Oscilloscope-p/ds1054z.htm#.VS198HCkqrU (http://www.rigol-uk.co.uk/Rigol-DS1054Z-Digital-Oscilloscope-p/ds1054z.htm#.VS198HCkqrU)
Watch this space... :)
Quote from: JonB on 21:54, 14 April 15
Well, I have ordered one of these so I should be able to resume the search in due course.
http://www.rigol-uk.co.uk/Rigol-DS1054Z-Digital-Oscilloscope-p/ds1054z.htm#.VS198HCkqrU (http://www.rigol-uk.co.uk/Rigol-DS1054Z-Digital-Oscilloscope-p/ds1054z.htm#.VS198HCkqrU)
Watch this space... :)
A fine scope. Don't forget to "enhance" it when your 30 days are up ;)
Bryce.
Opinion is divided on the 100MHz bit, but full on memory use and all the rest are definitely a must have. Was going to see how I get on with default features. Might have waited until the warranty was up but its 3 years!
The "liberation method" for the DS doesn't require opening the device and can be easily un-done, so Warranty isn't an issue.
Bryce.
The service manual has the following timing chart for the FDD (see attached image). I found The RDD signal on the PLL circuit diagram, but I don't know where the other signals are located. Are they aliases for known signals (FDC pins I imagine)?
The data going to the disk can be measured on pin 30 of the 765. Data coming from the disk can be measured on pin 23. You shouldn't need more than that. U2 could be referring to an IC, but the schematics you posted haven't used "U" numbering on the ICs.
Bryce.
U2 refering to 74LS112, it is phase detector with it's outputs pin 5 and 9. I think that "VFO CLK/2" is erratic, and should be "VFO TP2" (500kHz).
There is no CLK/2 = 1MHz signal in this phase detector.
Your diagram shows phase regulation process. To see that on real circuit, you need 2 channel scope synchronised with TP2 clock. Phase regulation is dynamic process, and always changing. In this case it depends on disc revolution (rotation?) stability. So actually this TP2 clock will not be exact 500,000kHz, but will be drifting around 500kHz. It is still chaseing Read Data frequency and phase.
Thanks kevin.c
What or wher are the other traces do you think? I have a 4 channel DCO on its way so I should be able to make these measurements, but only if I know where to put the probes..
JonB, for the final test of this FDC PLL I would treat it as black box and just check if it works correctly or not.
Connect the first probe to output clock TP2 500Khz or 250kHz. Set o-scope synch to first CH ONLY!
Connect second probe to Read Data (30) or Output Read Data (pin 23).
Set floppy to read still one track to get valid and stable Read Data stream. The PLL clock should lock.
Observe on the screen if CH2 Read Data bits are stable in frequency and phase against CH1 clock pulse.
Of course bits must change, that's the data stream, but it should be clearly visible if they are synchronized or not.
Right. Should get the scope in a couple of weeks, then I can "scope it out,dude"!
Looking forward to it (scope is right complicated though)!
Is it your first scope? Do you know the basics? If not, there are some really good documents and videos on the net that I'd recommend you read/watch. Scopes can be very deceiving if you don't know how to set it up properly.
Bryce.
Yes, first scope. Cannot wait. Fortunately it has an Auto feature so I should at least be able to see the waveforms, but feel free to recommend online resources. There does not appear to be a "Scopes for Dummies" book (I prefer books to online resources for reference materials).
Ah yes, also I am shopping around for a solder station - any recommendations?
Quote from: Bryce on 20:34, 16 April 15
.........Scopes can be very deceiving if you don't know how to set it up properly.
Bryce.
It is quite right! When you all set to auto - the scope, specially digital one - will try to show waveforms as clean and stable as possible. In our FDD PLL case,
you must recognize if it is stable because of good scope digitalisation or PLL properties. It is not so obvious and needs some experience.
One has to start somewhere...
The Auto button is useful for your first experiments, but you need to learn what's really happening, so try to move away from using Auto as soon as possible. My recommendataion is to experiment with known signals and learn how the different adjustments affect what is displayed.
A good example of why Auto is not good: If I measure a clock signal of 4Mhz which is full of noise at 60Mhz (which is the problem and what you want to find in this example). Hitting the Auto button will attempt to show a clean 4Mhz signal. The horizontal and vertical will be set correctly, but it will also turn on the 20Mhz bandwidth limit which hides the 60Mhz noise and hence you don't see the problem. If you were manually looking for this problem, you'd have left the bandwidth limit high and probably turned up the persistance value too.
I don't know of any "physical" books about scopes, but I can put together a list of links to pdf files which you could read (or print if you really want to).
As far as irons are concerned:
- Buy one that allows you to set the temperature and displays it too.
- Don't buy one with a handle / tip big enough to weld a ship together. The tip should be a chisel tip and about 2mm wide at the end.
- Don't buy a combi version that includes a rework station - If you need both, then buy two separate units.
- Buy a known brand so that you can be sure you can still buy new tips in the future.
Personally I prefer Ersa, but Weller, Hakko and many other companies do good irons too.
Bryce.
Edit: For anyone just starting out with there first scope, here's a whole collection of documents worth reading. Although they are from Tektronix, the information is valid for any scope: Oscilloscope Tutorial | Tektronix (http://www.tek.com/learning/oscilloscope-tutorial)
Hi Bryce
Sage advice as always, thanks!
On the Rigol I read you use auto to get to a known state. The display is all over the place otherwise. But I will find out once I have it.
I ordered a Hakko FX-888D in "CBeebies" livery (blue & yellow).
I've never used Hakko personally, but I'm told they are good irons.
Auto button doesn't really bring you to a "Known state" unless you know what state the scope got to. When you get used to the scope you'll find that it's better to know exactly what you are watching rather than what the scope thinks you want to watch.
Bryce.
OK, I have it at last. Took six weeks, because they are so popular. Damned fine 'scope it is too!
I have measured the monoflop at TP1 as shown in the manual and it is showing a pulse width of 3uS. It is supposed to 1uS or as near as possible. Adjusting the trimmer 4713 brings it down, but only to 2.77, however it is an uneven waveform with the gap between falling and rising roughly 33% the gap between rising and falling. So I am thinking that the smaller gap is the one I need to calibrate, and sure enough I can get it to 1uS. Hurrah.
But... It is still not working, unable to read disks. So I'm wondering, what should I check next? I do have the timing diagrams for the FDC and I will take a look.
Yes, it's a negative pulse, not a positive. The "gap" you're talking about IS the pulse and it looks fine.
Bryce.
Quote from: kevin.c on 10:21, 16 April 15
JonB, for the final test of this FDC PLL I would treat it as black box and just check if it works correctly or not.
Connect the first probe to output clock TP2 500Khz or 250kHz. Set o-scope synch to first CH ONLY!
Connect second probe to Read Data (30) or Output Read Data (pin 23).
Set floppy to read still one track to get valid and stable Read Data stream. The PLL clock should lock.
Observe on the screen if CH2 Read Data bits are stable in frequency and phase against CH1 clock pulse.
Of course bits must change, that's the data stream, but it should be clearly visible if they are synchronized or not.
So, if I trigger on the 500khz test point (Ch.1, Yellow) and try to see the read data (pin 23 on the FDC chip; Ch. 2, cyan) all I am getting is a narrow pulse (~120nS) that aligns with the 500Khz wave forms. Can't see any actual data. Aren't these supposed to change with 0 / 1 ? And I see this even when it's not reading (shown below).
What Data seperator does the controller use? Have you read its input?
Bryce.
Sorry Bryce, I don't understand what you mean by that. It's a uPD765 controller.
In looking at the timing diagram, I am not sure where the measurement points are that correspond to some of the timing signals shown. I assume RDD is pin 23 of the FDC, but if that is the case, all I am getting is a stream of 1s. Could you help me identify the test points for the signals READ DATA(MFM), SHAPED DATA, VFO CLK/2, No.5 U2, No. 9 U2?
I'm looking at !RD on pin 2. According to the timing chart it goes active low during the read operation. All I can see is noise right now, even when reading. Does that tell you anything?
..other than I don't yet know how to use my new 'scope, ha ha!
Ah silly me, !RD is for transferring to the system data bus, not grabbing stuff from the drive read pin. Duhh..
The signal from the disk drive isn't fed directly to the µPD765, it has to go through a Data seperator circuit/chip first. What chip is used in your case (the CPC for example uses an FDC9216 or later an SED9420 to do this). What IC is used in this case and what signal are you getting at the input to this chip?
Bryce.
..and RDD (pin 30 in the Shugart drive interface) is shown on the PLL schematic. So...
Yes, it's showing data and I can see it getting fed into the PLL circuit bottom left.
The other input is the SYNC pulse which looks like a sawtooth at 25-27Mhz. Disconnecting the drive makes it bigger; I'm thinking it is noise.
SYNC is also shown on the PLL circuit coming in from the right hand side. Without it, nothing of the RD signal makes it past the first gate of 7414.
Sure enough, there is nothing coming out but a sawtooth. So should I conclude that the issue is with the SYNC line?
Quote from: Bryce on 17:30, 14 May 15
The signal from the disk drive isn't fed directly to the µPD765, it has to go through a Data seperator circuit/chip first. What chip is used in your case (the CPC for example uses an FDC9216 or later an SED9420 to do this). What IC is used in this case and what signal are you getting at the input to this chip?
Bryce.
Not sure - it should be on the FDC schematic. I think it is that discrete logic bottom left which is marrying up SYNC with RD pulses. As you can see I can't detect anything on the SYNC line but some 27Mhz sawtooth, so I think it may be not connected properly. Going to check it for continuity.
More and more confusing. FDC Pin 24 isn't reading anything and is showing a logic low with a probe, even when attempting to read. I think this indicates an issue with the FDC. Anyone care to comment?
More info from an application note for the FDC (https://ia601607.us.archive.org/14/items/bitsavers_necdatashe79_1461697/uPD765_App_Note_Mar79.pdf) that explains how to build an interface:
QuoteIn the Read mode, the VCO Sync signal goes true after the R/W head has been loaded and the head settling time (head load time) has elapsed. (See bottom of Figure 7.) The VCO Sync goes false between the 10 Field and the Data Field; and after the Data Field. This is done to blank out discontinuities which appear in these gaps when the Write current is turned on and off. When VCO Sync is true, valid data is coming off the diskette and the data recovery circuit does not have to be configured to accommodate any abnormal conditions.
So it won't be high all the time.
Additional info: Head load is showing pulses (very sloooow ones). Since this is related to the VCO Sync I thoiught I'd better check it, but it looks OK. Again, though, there is no activity on the VCO line.
To avoid all this back and forth, can you patch together a schematic of the complete system, from the drive head up to where it's outputted as 8-bit data. That way I/we can see exactly what's happening and tell you what you should be expacting where.
Bryce.
OK Bryce, it'll take a short while, though. The schematics in the service manual are a little fragmented.
Do you really want it from the drive heads? The drives are Teac F55 and I know they work. I used one to read the P2000C's boot and application disks on my PC with 22disk144.exe with no problems (once I'd found the correct parameters for the P2000C's format of course).
Bearing this in mind I propose to start it from the 34 pin connector (standard Shugart) for now. If we need to go upstream of that I can dig out an FD55 service manual. Sounds good?
Cheers
JonB
Oh, by the way, do you think that the FDC may be suspect given that it is not outputting a VCO signal? (I shall also check for a short to ground somewhere..!)
From the 34way header is fine.
Bryce.
Hi Bryce
I don't have a PDF editor so I am going to have to refer you to the full document:
http://electrickery.xs4all.nl/comp/p2000c/doc/P2000C-SystemRefServiceManual.pdf (http://electrickery.xs4all.nl/comp/p2000c/doc/P2000C-SystemRefServiceManual.pdf)
I really would have preferred to paste the schematics into a new PDF.
Anyway, the main board schematics start at page 134 and the FDC description including detail of PLL, FDC and timing starts on page 87.
The diagram on page 134 shows the board layout; the PLL and FDC connector are at bottom right on the bit of the PCB sticking out. The full schematics are on pages 87-90, and the full FDC circuit is on page 89 (with PLL bottom left).
Regards
JonB
I've got my desoldering station and spent a few minutes swapping the FDC out. I put it into a 6128 (socketed of course!), and it worked perfectly. So the FDC itself is not the problem here. And here's me hoping it was! Drat and blast.... :(
OK, first off I want to look at the 74LS00 that is matching the RDD and VCO SYNC signals together, then the 250khz signal:
[attachimg=2]
I get some odd looking waveforms.. Let me show you.
This is the RDD input at 7414 Pin 12. Looks like there is some data there.
[attachimg=1]
The VCO input at test point 416 (7414 pins 1 and 2) is just noise at a very low voltage. When I attempt to read the disk, there is a tiny amount of activity but not enough to call it a TTL signal. Here's the best picture I have of it.
[attachimg=3]
The output of the first gate at pin 11 looks suitably dodgy.
[attachimg=5]
My first question is this: Shouldn't the output of this gate be clean (like the RDD signal but better shaped)?
Here we have the index mark at pin 17 of the FDC
Well.. I swapped out the LS7400 and I'm sorry to say it is not the cause of the problem.
Worth a try though..
Hate to do this, but ** BUMP **
I'm out of ideas.
Hi JonB,
sorry, I was away for a few days. I took a look at the schematics now. Can you tell me what signal you are getting on pin 12 and pin 13 of the 74LS14 (IC 7434). This is the gate that should be "squaring-off" the data signal.
Bryce.
Hello Bryce
The RDD signal is shown in the yellow trace in one of my previous posts (this one Interpreting uPD765 FDC result bytes (http://www.cpcwiki.eu/forum/hardware-related/interpreting-upd765-fdc-result-bytes/msg100221/#msg100221)). It's taken at test point 421 which is pin 12 of the 7400 (basically the same point you mention). As you can see it does appear to have data.
Now I am on holiday I have lots more time to investigate, so I should be able to give better answers.
Cheers
JonB
Yes, but the signal on pin 13 is much more important. If that's a flat line or permanently 5V, then the 74LS14 is dead. We (you) have to trace the signal from it's source to it's end point to find out where things are going wrong.
Bryce.
Pin 13 is the RDD input signal. I have looked at that an there is a pulse coming in from the drive. Hang on, I'll get a trace for you...
ignore, i got all the attachments mixed up
OK, here we go. In the following images, the blue line is the trace at IC7434 pin 13 (input, RDD signal from drive), and the yellow trace is at pin 12 (output of first gate).
Not reading. Lots of noise there!
[attach=2]
Reading. You can see the negative pulses from the drive and the resulting output from the first gate, but there does appear to be quite a lot of noise in the output.
[attach=3]
Let's have a closer look. See the noise at the top of the yellow waveform? This doesn't look like a sane output. I thought it was supposed to clean the signal right up...
[attach=4]
So can we conclude that IC7434 is damaged? It's a Schmitt trigger (something I am just reading about) and from what I see of the datasheet, the output is all wrong. In fact, electrically it looks like a resistor from these traces, because it appears to be attenuating the input signal without shaping it. Isn't it supposed to invert the input signal as well?
OK, this looks more promising.
Same traces as before, but I can see now the LS14 doing its job.
[attach=2]
This is the result of me desoldering it and fitting an IC socket. Dry joint?
I was just reviewing the thread, and the error reported by the FDC is that the RDY signal changed state (presumably unexpectedly). So I thought I'd have a look round the RDY circuit.
[attach=2]
Now, this is pin 35 on the FDC and it is an input (to the FDC), yet here we see it feeding the input of a 74LS175 flip flop. Pin 4, actually, which the datasheet says is D0 but it is marked as 1D on the schematic. In fact the markings on the schematic don't match the chip much at all.. Hmm. So I went to the board, and both this chip and the one below it are missing, but there is no evidence of desoldering. The pads are all intact and all full of solder, as if it was flow soldered at the factory like that.
Time to do some continuity checks, but honestly I would expect to see some - any - evidence (like scratches round the pads, or visible holes instead of filled-in pads) that these chips had been removed after manufacture.
I checked the amendment documents, of which I see only two on the "electrickery" web site that holds all the documentation (here: Documentation for the Philips P2000C computer (http://electrickery.xs4all.nl/comp/p2000c/doc/index.html)). There isn't an updated schematic that shows these missing chips removed..
Another thing I don't understand is why the Shugart /RDY signal (on line 34 of the FDD cable) is marked as "2-Side" and appears to feed FDC WP/2-side pin via the LS244 (IC7454) buffer. Maybe it is using the drive's RDY to indicate the drive isn't double sided when the FDC requests a read on side 2 with a 1 sided drive is connected. But RDY should also be connected to the RDY line of the FDC I would have thought.
WP/2-Side is showing a signal, though...
[attach=2]
A pair of little pulses then a big one which is 1.2mS wide.
Perhaps the FDC's RDY it is being forced high by the resistor pack (4709, shown below), which would mean it is seeing a ready drive all the time?
[attach=3]
Edit: Yes, it is. Pin 35 of the FDC is showing high all the time. So I think the status "ready signal changed" is misleading.
I had a thought.
To get the result set above, I am asking the P2000C's monitor to read the content of track 0 on side 1 of the disk. It never completes the operation. And I now think it is because something else, prior to reading, is failing. In the FDC data sheet it explains how a read should be conducted. You issue recalibrate command (moves head to drive zero), then seek to the track to read, then read. So I think that, although it is seeking and recalibrating (head moves), there is an error or missing signal somewhere that prevents the read command being called by the monitor.
When you issue the read track command to the monitor, it executes the command continuously until you hit the escape key. When reading a higher track (say, Track 10), it zeros the head prior to each iteration of the command. I think this is the FDC recalibrate command being executed. Then, the dead seeks to track 10. After this, the error state is reported. So I would be checking the result the seek operation next.
It's a pity I don't have the monitor source, because with that I could work out what FDC operations the "read track" command is using, and perhaps where it fails.
OK, it's "pseudo-random parts swap" time.
I've swapped out the following ICs:
IC7414 74LS00, used in the input to the data separator.
IC7451 upd765, the FDC itself.
IC7454 74LS224, used to buffer the incoming FDD control lines (2,26,28,34), including RDY.
IC7452 74LS04, inverter that is used all over the place, including FDD control lines.
None of this has made any difference, I'm still getting the same error codes back when trying to read a disk.
Odd question, but is anyone reading this, or am I posting to myself?
I'm still reading, but I'm really beiginning to think that you are either testing the drive wrong or the drive itself has failed. Have you tried the drive in a different system? Have you tried a different drive in this system?
Bryce.
Quote from: JonB on 13:49, 27 May 15
Odd question, but is anyone reading this, or am I posting to myself?
I am.. Not that I can help much.
Quote from: Bryce on 14:12, 27 May 15
I'm still reading, but I'm really beiginning to think that you are either testing the drive wrong or the drive itself has failed. Have you tried the drive in a different system? Have you tried a different drive in this system?
Bryce.
Thanks Bryce, I really did think I was going mad... ???
Anyway...
I have tried both drives in drive 1 slot (DS0) with and without the terminator resistor pack fitted and on both drive connectors (the cable is soldered to the board but it's got two edge connectors fitted for drive 1 and 2 (DS0 / DS1 repsectively). It doesn't make any difference, I am still getting C0 00 00 00 10 00 FF with every read track, and also with write track as well.
Using IMGDSK I created a copy of the P2000C system disk downloaded from some web site a while ago on a fresh floppy (3M, new old stock). The parameters are: Double Step=DISABLE, 300Khz = 250Khz. The new disk is readable using 22DSK144.COM (another great disk utility) using the PH2 (Philips P2012) settings. This is with one of the P2000C's drives plugged into a PC (AT spec, Win98 only and running in DOS mode), configured as a 3.5" 720k disk. Not only can I read the new disk with this, but I can also read every one of the old disks that came with the machine. Or rather, I can read the directories; I haven't tried pulling actual data off any of them yet, but I have formatted and written to another NOS disk, and read it back.
So I would have to say that given I can use one of the FD55Fs in the PC successfully, and that same drive doesn't work in the P2000C, the only conclusion to be drawn is that the disk drive is OK.
Just to be sure, I have connected another set of 3.5" floppies to the P2000C. Had to desolder the old drive cable and fit a set of header pins, then I could plug the 34 way female IDC connector straight into it. I copied a disk image using the known working settings on IMGDISK and verified with 22DSK144 and attempted to read it with the P2000C.
No joy.
I have a pair of dual drive BBC micro units too (they are the same spec) but I'm pretty sure they won't work either.
[Edit: Nope, they don't work. So that is a total of eight different drives I've tried with it. Must be the board.]
Sorry, but I've really run out of ideas, without having the device here it's difficult to diagnose it any further :(
Bryce.
Well, this is fun. Here is some test code for the FDC.
;----------------------------------------------------
; Project: floptest.zdsp
; Main File: floptest.asm
; Date: 30/05/2015 12:20:09
;
; Created with zDevStudio - Z80 Development Studio.
;
;----------------------------------------------------
CONST equ 0F606h ;Console status
CONIN equ 0F609h ;Console input
CONOUT equ 0F60Ch ;Console output
LIST1 equ 0F60Fh ;Printer output
COMOJP equ 0F612h ;Com output
COMIJP equ 0F615h ;Com input
DPBADDR equ 0FFD0h ;Driver parameter block address
DPBDRV equ 00h ;Drive
DPBTRK equ 01h ;Track
DBPSEC equ 03h ;Sector
DPBHEAD equ 04h ;Head (0 or 1)
DPBRWB equ 05h ;Read/Write buffer address
DPBLEN equ 07h ;Buff length -1 (after read; before write)
RDS equ 09h ;Read sector routine addr
WRS equ 0Bh ;Write sector routine addr
STEP equ 0Dh ;Seek to track routine addr
RECAL equ 0Fh ;Recalibrate head routine addr
BOOT equ 011h ;Boot routine addr
LISTAT equ 013h ;List status routine addr
PRTAB equ 015h ;Print table addr
PRWAIT equ 017h ;Print wait time in 4sec units
PRSTAT equ 018h ;Printer status byte; 0=err
PRCONT equ 019h ;If 0, no message if printer not ready (?)
BOOTDR equ 01Ah ;Boot drive (0, FF or 1)
DSKFLG equ 01Bh ;Internal disk flag
DMSTAT equ 01Ch ;DMA shadow byte
HDERSU equ 01Dh ;XEBEC err routine addr
DSKTR equ 01Fh ;00, C9 = Standard track numbering
;24, C9 = old Philips track numbering
PRSCR equ 021h ;Print screen routine addr
MSWBYT equ 023h ;0 if ROM, 2 if RAM
JMPC3 equ 024h ;C3 for jump (?)
TINEX equ 025h ;Address of external timer interrupt
KSTAT equ 027h ;Key status, 0 if no key currently pressed
KBYTE equ 028h ;Last depressed key
CLOCK equ 029h ;60hz clock (counter?), 4 bytes long
RESULT equ 02Dh ;Floppy result bytes, 7 bytes, starts at FFC4
RWBUFF equ 08000h ;disk buffer
org 4000h
LD DE, STEP
call JUMP
RET
;DEFB "GETOFF"
GETOFF: LD HL,(DPBADDR)
ADD HL,DE
RET
;DEFB "JUMP"
JUMP: CALL GETOFF
LD E,(HL)
INC HL
LD H,(HL)
LD L,E
JP(HL)
RET
;Setup for read track
SEEK: ;DEFB "READ TRACK STARTS"
LD HL,(DPBADDR)
LD (HL),00h ;Drive 0
INC HL
LD(HL),0AH ;Track 10
INC HL
INC HL
LD(HL),05H ;Sector 5
INC HL
LD(HL),00h ;Head 0
INC HL
LD DE, RWBUFF
LD(HL),D
INC HL
LD(HL),E
INC HL
LD(HL),0FFh
INC HL
LD(HL),00h
RET
What is does is use the low level P2000C BIOS driver routines that are stored on the Driver Parameter Block (DPB). You can see the form of the DPB in the block of equates at the top of the file. There are a couple of helpers:
GETOFF - get offset from DPB start address, given an offset in DE. Return offset in HL.
JUMP - Call subroutine whose address is located at the DPB offset given in DE.
In case you are wondering why they are separate, I will be using GETOFF to get/set the DPB values that aren't vectors.
SEEK - Sets up a sector address in the DPB (I wrote this before GETOFF so it doesn't use it).
So, first I called RECAL and the heads were moved to TRACK 0. Result bytes were 20 00 00 00 00 00 00 00 (ST0, D5 "Seek End"). All good, then.
Then I amended the command to a STEP. I moved the head to track 10 as shown in the SEEK code. The head moved (to 10) and I examined the result bytes in the DPB. They were 20 20 00 00 00 00 00. Which means ST0: D5=Seek End (good), ST1: D5=Data Error (bad).
Finally, I amended the command to read the specified sector, executed and got the familiar C0 00 00 00 00 00 00 (ST0: D6/7=Drive RDY state change).
What I find a little odd is that STEP should be giving any result in ST2 at all. The FDC datasheet shows that when you do a seek, it moves the head but the result bytes are unchanged. Yet here we see an update to the first and second result bytes, which I find odd. Maybe the BIOS seek routine is trying to acquire some data... so I will disassemble it to find out, if I can locate it (the address is not in ROM, as it gets copied out at bootup). I think FF03h. Edit, STEP is one of the ROM resident commands, at 027Ch. Likewise, RECAL at 0299h and RDS is in upper RAM at FD45h.
Edit 2: Although the datasheet's command summary table says seek doesn't give results, the description states that if the disk is not ready at the start of command execution, it will set ST0 D7/D6 to 0/1 (abnormal termination of command) and D3 to 1 (Drive Not Ready flag) which would be 48h.
Interesting. I noticed that WCK isn't getting a signal, but the datasheet on CPCWiki says:
QuoteWCLK (Write Clock)
The WCLK input sets the data write rate to the FDD. It is
500 kHz for FM, 1 MHz for MFM drives, for 8 MHz operation
of the FDC; 250kHz FM or 500 kHz MFM for 4 MHz
FDC operation.
This signal must be input for read and write cycles
WCLK's rising edge must be synchronized with CLK's
rising edge, except for the uPD765B.
So this sheet is implying I need a valid WCK signal for
read operations. The fault here is with IC7486 which divides the system clock down to what I assume is 250khz and ensures it is aligned.
[attach=2]
Where it says 500khz, that is as measured, and it's a fairly clean square wave (so the right hand flipflop and intervening gates seem to be working). But at the 250Khz point, there is something unexpected. It is a LOW signal (0v with a bit of noise). Pins 10 and 12 are HIGH as expected; and the 2Mhz signal at pin 13 and 1Mhz signal at pin 3 are both present and correct (in phase), so I think the second flipflop (on the left) has failed. The part is on order...
And here is some scope porn...
Yellow is the 2Mhz trace.
Cyan is the 1Mhz trace.
Magenta is the 500Khz trace (5v so it's a bit flatter than the others which are @2v).
Hmm, I think I got that wrong. The expected trace at pin 9 of the 74LS74 is a 500khz pulse with width of ~200ns, like this:
[attach=2]
..which is what I got when I replaced the part. Serves me right for not reading the data sheet fully. Oh well.
Anyway, having replaced the chip I reconnected the PC and started Hyperterm. Lo and behold...
PHILIPS P2000C 63K CP/M 2.2
KEYBOARD UK/NL, VIDEO UK/NL, PRINTER EMPTY
A:640K-FL1 B:640K-FL2
A>dir
A: CPM61 COM : CPM62 COM : CPM63 COM : CBIOS61 COM
A: CBIOS62 COM : CBIOS63 COM : ABASIC COM : CHESS COM
A: CONV COM : ZUID1 : ZUID2 : ZUID3
A: ZUID4 : allard BAS : STAT COM : UTIL COM
A: WSMSGS OVR : WSOVLY1 OVR : WS COM : WS INS
A: UTIL MSG : CPYDSK COM
YES!!!
Congratulations, and as a bonus you got to learn a bit about your new scope too :)
Bryce.
Now just the terminal board to fix. ;D
Thanks for your help & advice!