Role of the 74LS153 Multiplexer During Memory Access

[Rabs]

I am trying to understand the role of the 74LS153 Multiplexer during memory access and there is something I don't understand. I think I am missing something obvious but cannot see what.

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I understand that the Gate Array generates the signals /CPU and /CASADDR. So I guess /CPU will be low and /CASADDR will be high when accessing the row address in memory.

I understand that the high byte of the Address is first latched into memory (RAS) followed by the low byte (CAS).

What I don't understand is that from the above schematic A15 are A14 (the high order bits in the address) are only selected when /CPU is low and /CASADDR is low. I expected /CASADDR to be high. This is the bit that I am getting confused about 

Looking at the truth table for the 74LS153, the output pins pin 10 (A15) and pin 6 (A14) follow the input pins pin 2 /CPU and pin 14 /CASADDR when they are both low.

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I must be missing something obvious but I cannot see it 

Any help much appreciated.

[eto]

In the CPC the low byte is RAS and the high byte is CAS. You can see that in the schematics on one of the mixers.

[Rabs]

Thanks for confirming.

I guess somewhere in my head, I was stuck on RAS being the high byte of the address, even though the schematic told me different  

And I guess the arrangement of the address signals does not matter as long as the CPU and CRTC match?


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[Bread80]

Also remember that RAM doesn't care which address line is which. In other words as long as you use the same address to store data as you do when you retrieve it everything will work correctly. When doing board layout with RAM ICs it's common to rearrange the address lines to make the routing more convenient.

Contrast that with a ROM chip. The ROM is programmed elsewhere and the address sequence used to read the data must use the same addresses as that used to program it.

[Rabs]

Also remember that RAM doesn't care which address line is which. In other words as long as you use the same address to store data as you do when you retrieve it everything will work correctly. When doing board layout with RAM ICs it's common to rearrange the address lines to make the routing more convenient.

Contrast that with a ROM chip. The ROM is programmed elsewhere and the address sequence used to read the data must use the same addresses as that used to program it.

Thanks, by the way loved your page on this subject. Thanks

[McArti0]

If the addresses and data were mixed up in the rom, it would be very fun to reverse engineer the chip itself. 

[djaybee]

The apparently weird ordering has a reason: while it indeed doesn't matter semantically, it's important for the DRAM refresh where some access must happen on each row within a specified interval (the chips on one of the common CPC motherboards photos require 2ms). If there exists some reason why regular memory accesses already accesses all rows, there's no need for a separate refresh mechanism, and, in the CPC, reading the framebuffer (mostly) accomplishes that goal given the careful choice of inputs to the multiplexers. Note that A0 must be a column address, because the Gate Array generates 2 consecutive accesses per CRTC "character" that must land in the same row. Notice how on 6128 RAS gets set to both memory banks, and only CAS gets selectively routed to one or the other.