Quote from: Bread80 on Yesterday at 22:59Yup, so I would check the traces first. You can create all sorts of odd repeating patterns.Quote from: Rabs on Yesterday at 22:32How does the CRTC come into play with addressing lines, could it be that if one of the tracks between the CRTC and multiplexers was broken that the same adress lines would be repeated when addressing the memory for the screen display and hence repeat? See Noel's video, mentioned above.Yup. That's pretty much the issue here. But the repeat in this instance is every successive byte. So we're talking about address line A0. A0 is driven directly by the GA, it's the signal whose full name is MA0_CCLK - "address line zero, CRTC clock".
I've no idea why they didn't just clock the CRTC at twice the frequency though. I believe it's capable. Maybe there's a limitation on how it can be programmed? Maybe it would have required an extra signal from the GA? Maybe the CRTC is too slow to update between the two video bytes?
Quote from: Rabs on Yesterday at 22:32How does the CRTC come into play with addressing lines, could it be that if one of the tracks between the CRTC and multiplexers was broken that the same adress lines would be repeated when addressing the memory for the screen display and hence repeat? See Noel's video, mentioned above.Yup. That's pretty much the issue here. But the repeat in this instance is every successive byte. So we're talking about address line A0. A0 is driven directly by the GA, it's the signal whose full name is MA0_CCLK - "address line zero, CRTC clock".
Quote from: eto on Yesterday at 20:06I'm a bit lost here. How can the address multiplexer have an impact on the data bits? (except for selecting the wrong address of course)It's interesting to note that A0 (CCLK) is the only bit which changes between the two bytes. Suppose the multiplexers are running a little slow. That could mean A0 hasn't fully settled by the time ~CAS transitions low and the DRAM's address decoders start working. The late transitioning signal could, perhaps, mean that different DRAM's are working off of different values for A0. So, maybe, some of the chips are return a value for A0=1 and some are returning a value for A0=0. Possibly the address decoding is incomplete and they may be returning data for a completely different address.
Quote from: BSC on Yesterday at 20:20I have a few Maxell disks which are still shrink-wrapped and in 100% mint condition. Might sell them for a completely excessive price10 of them boxed, original. Perhaps I would swap for a Porsche 959. :-)
Quote from: McArti0 on Yesterday at 15:56No multiplexer can swap bits.
Quote from: Bryce on Yesterday at 18:37I fully agree,
Quote from: Xyphoe on Yesterday at 17:58Oh that's brilliant! Thank you!! <3Yes, the list is updated regularly, once a year
(By the way, I was getting my list and checking from the CPC Wiki page as per the 1st post on this thread - https://www.cpcwiki.eu/index.php/Converted_GX4000_Software - it's not listed there so I guess the list isn't maintained regularly)
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