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#1
Quote from: Bread80 on Yesterday at 22:59
Quote from: Rabs on Yesterday at 22:32How does the CRTC come into play with addressing lines, could it be that if one of the  tracks between the CRTC and multiplexers was broken that the same adress lines would be repeated when addressing the memory for the screen display and hence repeat? See Noel's video, mentioned above.
Yup. That's pretty much the issue here. But the repeat in this instance is every successive byte. So we're talking about address line A0. A0 is driven directly by the GA, it's the signal whose full name is MA0_CCLK - "address line zero, CRTC clock".

I've no idea why they didn't just clock the CRTC at twice the frequency though. I believe it's capable. Maybe there's a limitation on how it can be programmed? Maybe it would have required an extra signal from the GA? Maybe the CRTC is too slow to update between the two video bytes?
Yup, so I would check the traces first. You can create all sorts of odd repeating patterns.

This is IC113 PIN 3 on my test board.

You cannot view this attachment.

I will try IC105 PIN 4 tomorrow and see if I get the same pattern.
#2
Quote from: Rabs on Yesterday at 22:32How does the CRTC come into play with addressing lines, could it be that if one of the  tracks between the CRTC and multiplexers was broken that the same adress lines would be repeated when addressing the memory for the screen display and hence repeat? See Noel's video, mentioned above.
Yup. That's pretty much the issue here. But the repeat in this instance is every successive byte. So we're talking about address line A0. A0 is driven directly by the GA, it's the signal whose full name is MA0_CCLK - "address line zero, CRTC clock".

I've no idea why they didn't just clock the CRTC at twice the frequency though. I believe it's capable. Maybe there's a limitation on how it can be programmed? Maybe it would have required an extra signal from the GA? Maybe the CRTC is too slow to update between the two video bytes?
#3
May I also suggest to check if the logic chips are of the same time (that is LS, or HC)?

They have slightly different TTL activation levels and that can cause problems.
#4
Quote from: eto on Yesterday at 20:06I'm a bit lost here. How can the address multiplexer have an impact on the data bits? (except for selecting the wrong address of course)


It's interesting to note that A0 (CCLK) is the only bit which changes between the two bytes. Suppose the multiplexers are running a little slow. That could mean A0 hasn't fully settled by the time ~CAS transitions low and the DRAM's address decoders start working. The late transitioning signal could, perhaps, mean that different DRAM's are working off of different values for A0. So, maybe, some of the chips are return a value for A0=1 and some are returning a value for A0=0. Possibly the address decoding is incomplete and they may be returning data for a completely different address.

We're in the world of gate delays and nanosecond timings. Electrical signals travel at the speed of light, so the signals travel 30cm in a single nanosecond, and signals take a moment or two to settle into a new state. The distance between the DRAM IC could easily result in different chips sampling different values if the transition and bouncing happens at the wrong moment. This is the reason the world abandoned parallel interfaces in favour of serial ones.

I believe the correct term is 'metastability' for signals getting sampled when they are between states.

The above is just supposition, and the answer could be something entirely different, but I'd suggest it's plausable.

And I'd second Byrce's suggestion to check the resistors. They're in there to improve the settling time of the signals and it's very possible an issue with them could cause such issues.
#5
How does the CRTC come into play with addressing lines, could it be that if one of the  tracks between the CRTC and multiplexers was broken that the same adress lines would be repeated when addressing the memory for the screen display and hence repeat? See Noel's video, mentioned above.
#6
Quote from: BSC on Yesterday at 20:20I have a few Maxell disks which are still shrink-wrapped and in 100% mint condition. Might sell them for a completely excessive price  ;D
10 of them boxed, original. Perhaps I would swap for a Porsche 959. :-)
#7
I have a few Maxell disks which are still shrink-wrapped and in 100% mint condition. Might sell them for a completely excessive price  ;D
#8
Quote from: McArti0 on Yesterday at 15:56No multiplexer can swap bits.
Quote from: Bryce on Yesterday at 18:37I fully agree,


I'm a bit lost here. How can the address multiplexer have an impact on the data bits? (except for selecting the wrong address of course)

#9
C
Games / Challenge my Bluff, the 1984 q...
Last post by cwpab - Yesterday at 19:41
CPC Game Reviews just gave an unexpected 7/10 to a 1984 quiz game that can be played by up to 6 players.

I'm tempted to try this one...


This is the link to the review, but I warn you: don't read the last sentence as nich spoils the answer to the question of the screenshot!
#10
avatar_iXien
Games / Re: Converted GX4000 .cpr - Th...
Last post by iXien - Yesterday at 19:05
Quote from: Xyphoe on Yesterday at 17:58Oh that's brilliant! Thank you!! <3 

(By the way, I was getting my list and checking from the CPC Wiki page as per the 1st post on this thread - https://www.cpcwiki.eu/index.php/Converted_GX4000_Software - it's not listed there so I guess the list isn't maintained regularly)
Yes, the list is updated regularly, once a year :P . The last update was on March 11, just after the Time Scanner patch. That's why you can't find the games patched after this day for now.

We will see what we can do with your 2 other requests ;)
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