Changes
8255
,/* PPI Port B */
== 8255 Part numbers used in the CPC during its lifetime ==
* Mitsubishi M5L8255AP-5 [https://www.cpcwiki.eu/imgs/8/80/MC0001A-v2-components.jpg Source]* NEC D8255AC-2[https://www.cpcwiki.eu/imgs/d/da/Amstrad_CPC464_Z70200_MC0003A_PCB_Top.jpg Source]* NEC D8255AC-5[https://www.cpcwiki.eu/imgs/c/c6/CPC464_270100_MC0001A_PCB_Top.jpg Source]* Toshiba TMP8255AP-5[https://www.cpcwiki.eu/imgs/0/0d/CPC464_Z70100_MC0001A_PCB_Top.jpg Source]
All of these are almost identical in their operation. It According to Kevin Thacker, it is possible to detect each version by writing and then reading from the ppi control i/o port. Each can give a different pattern of values that are read back. The KP580BB55A is a Soviet clone of the Intel i8255. It is used in the [[KC Compact]] and the [[Aleste 520EX]] clones of the Amstrad CPC computer. <br>
== The 8255 in the CPC ==
The [[8255 PPI chip]] is a general purpose input/output IC. This document will describe its role in the Amstrad CPC, CPC+ and KC compact systems. To understand its full functions please read the datasheet.
In these systems it is connected to the [[PSG|AY-3-8912 Programmable Sound Generator (PSG)]], keyboard, cassette recorder, the VSYNC of the [[CRTC|6845 CRTC ]] and the "busy" signal from the parallel port.
The PPI is selected when A11 of the I/O port address is set to "0", A9 and A8 then define the PPI function access (as shown below), A15-A12 and A10 should be "1" (to prevent conflicts with other hardware), A7-A0 are don't care. So, resulting Port addresses are:
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|''!I/O address''||''!/CS (A11)!A1 (A9''||'')!A0 (A8''||'')!Description''||''!Read/Write status''||''!Used Direction''||''!Used for''
|-
|&F4xx||0||0||0||Port A Data||Read/Write||In/Out||[[PSG]] (Sound/Keyboard/Joystick)
|-
|&F5xx||0||0||1||Port B Data||Read/Write||In||Vsync/Jumpers/PrinterBusy/CasIn/Exp
|-
|&F6xx||0||1||0||Port C Data||Read/Write||Out||KeybRow/CasOut/PSG
|-
|&F7xx||0||1||1||Control||Write Only||Out||Control
|-
|}
In the CPC+, the 8255 is integrated into the ASIC. The "emulation" is not complete and some functionality is not available. Please see the [https://cpctech.cpcwiki.de/docs/cpcplus.html Extra CPC+ documentation] for more information.
<br>
== Port Usage ==
* NOTE - If you are using the firmware, always return the operating modes and I/O state of the ports used to their settings below. The firmware expects the settings to be the same as given below and may operate incorrectly if they are not.
<br>
== PPI Port A ==
* for reading data from PSG all bits must be set to input (thereafter, output direction should be restored, for compatibility with the BIOS).
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|''!Bit''||''!Description''||''!Usage''
|-
|7-0||PSG.DATA||[[PSG]] Databus (Sound/Keyboard/Joystick)
|-
|}
<br>
== PPI Port B ==
* Input
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|''!Bit''||''!Description''||''!Usage in CPC''||''!Usage in [[KC Compact'']]
|-
|7||CAS.IN||Cassette data input||Same as on CPC
|4||LK4||Screen Refresh Rate ("1"=50Hz, "0"=60Hz)||Set to "1"=50Hz (but ignored by the KC BIOS, which always uses 50Hz even if LK4 is changed)
|-
|3||LK3|| rowspan="3" |3bit Distributor ID. Usually set to 4=[[Awa]], 5=[[Schneider]], or 7=[[Amstrad]], see See [[LK-selectable Brand Names]] for details.||Purpose unknown (set to "1")
|-
|2||LK2||Purpose unknown (set to "0")
|0||[[CRTC]] VSYNC||Vertical Sync ("1"=VSYNC active, "0"=VSYNC inactive)||Same as on CPC
|-
|}
{| class="wikitable"
|+ Distributor ID
!Bit 3
!Bit 2
!Bit 1
!Brand name
|-
|0
|0
|0
|Isp
|-
|0
|0
|1
|Triumph
|-
|0
|1
|0
|Saisho
|-
|0
|1
|1
|Solavox
|-
|1
|0
|0
|Awa
|-
|1
|0
|1
|Schneider
|-
|1
|1
|0
|Orion
|-
|1
|1
|1
|Amstrad
|}
* If port B is programmed as an output, you can make a fake vsync visible to the Gate-Array by writing 1 to bit 0. You can then turn it off by writing 0 to bit 0. It is fake in the sense that it is not generated by the CRTC as it normally is. This fake vsync doesn't work on all CPCs. It is not known if it is dependent on CRTC or 8255 or both.
* For more info on LK1-LK4 (and further LKs) see [[LK Links]]
<br>
== PPI Port C ==
* upper: output, lower: output
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|''!Bit''||''!Description''||''!Usage''
|-
|7||PSG BDIR(Bus DIRection)||rowspan=2|PSG function selection
|-
|6||PSG BC1||(Bus Control 1)
|-
|5||Cassette Write data||Cassette Out (sometimes also used as Printer Bit7, see [[8bit Printer Ports]])
|-
|3||rowspan=4|Keyboard line||rowspan=4|Select keyboard line to be scanned (0-15)
See [[Programming:Keyboard scanning]] for details
|-
|2
|}
{| class="wikitable"|+ [[PSG ]] function selection: {|{{Prettytable|width: 700px; font-size: 2em;}}|''!Bit 7''||''!Bit 6''||''!Function''
|-
|0||0||Inactive
|-
|}
<br>
== PPI Control ==
This register has two different functions depending on bit7 of the data written to this register.
<br>
=== PPI Control with Bit7=0 ===
[[File:8255 Control0.png]]
<br>
=== PPI Control with Bit7=1 ===
[[File:8255 Control1.png]]
<br>
== Group Modes ==
In some of these modes, port C is used as a control/status port for port A or B. It can be used to confirm when data transfer may take place, and reflect any other flags. The 8255 PPI is therefore supplied with the added option for the user to set or reset any individual bits in port C.
<br>
=== Mode 0 – Simple Input/output mode ===
[[File:8255 - mode-0.png]]
<br>
=== Mode 1 – Strobed Input/output or Handshake mode ===
[[File:8255 - mode-1.png]]
<br>
=== Mode 2 – Bidirectional Mode ===
[[File:8255 - mode-2.png]]
<br>
=== Port pins summary ===
[[File:8255 - Port pins.gif]]
<br>
== Programming Examples ==
</pre>
<br>
== Block Diagram ==
[[File:8255 Block Diagram.png]]
The PPI 8255 does not have a clock pin. It relies purely on control signals from the CPU to operate. It uses Read, Write, and Control signals to manage data transfers instead of a clock signal. This allows it to work effectively without needing its own clock input.
== Amstrad ASIC PPI == *The 8255 PPI is not emulated by the Pre-ASIC. These CPC’s CPCs have a real PPI chip and therefore behave like the first generation of CPC’sCPCs.
*The ASIC PPI does not support Group Modes other than Groupe Mode 0.
*On the ASIC PPI, Port B is always defined as input and Port C is always defined as output.
*On a real PPI chip, when the PPI control register is used (with bit7=1) to configure the ports, the output latches of all ports are reset to 0. The ASIC poorly emulates the PPI and does not reset these ports.
<br>
== Resources ==
* [[Media:Intel8255A_datasheet.pdf]] PPI Datasheet (Intel)
* [[Media:PPI M5L8255AP-5.pdf]] PPI Datasheet (Mitsubishi)
* [[Media:Programmable Peripheral Interface TMP8255AP-5.pdf]] PPI Datasheet (Toshiba)
* [https://github.com/jotego/jt8255 JT8255] Verilog implementation of the 8255 PPI
<br> == Links ==
*[http://en.wikipedia.org/wiki/Intel_8255 Wikipedia about the 8255ppi]
*[http://quasar.cpcscene.net/doku.php?id=assem:ppi Quasar PPI documentation (in french)]
[[Category:Electronic Component]][[Category:CPC Internal Components]][[Category:Programming]]
