Changes
Z80
,*[https://floooh.github.io/2021/12/06/z80-instruction-timing.html Detailed look at Z80 instruction timings with the help of a Z80 netlist simulation]
*[https://wikiti.brandonw.net/index.php?title=Z80_Instruction_Set Z80 Instruction Set on WikiTI]
== Registers==
{| class="wikitable"
|+ Z80 Registers
! Register !! Size !! Description !! Notes
|-
| B, C, D, E, H, L || 8-bit || General-purpose registers || Can form 16-bit pairs: BC, DE, HL
|-
| A (Accumulator) || 8-bit || Main register for arithmetic, logic, and data transfer || Often used in operations involving memory or I/O
|-
| F (Flags) || 8-bit || Condition flags:
* S (Sign)
* Z (Zero)
* H (Half-carry)
* P/V (Parity/Overflow)
* N (Subtract)
* C (Carry) || Flags affected by most operations
|-
| AF', BC', DE', HL' || 16-bit || Alternate register set || Swappable with primary registers for fast context switching
|-
| SP (Stack Pointer) || 16-bit || Points to top of the stack || Used for subroutine calls and interrupt handling
|-
| PC (Program Counter) || 16-bit || Points to the next instruction || Automatically increments as instructions execute
|-
| IX, IY (Index Registers) || 16-bit || Used for indexed addressing || Can be split into IXH/IXL, IYH/IYL for 8-bit access
|-
| I (Interrupt Vector) || 8-bit || Holds base address for interrupt mode 2 || Combined with external data to form an interrupt vector
|-
| R (Memory Refresh) || 8-bit || Increments after each instruction fetch to refresh DRAM || Only the lower 7 bits are incremented
|-
| IFF1 || 1-bit || Interrupt enable flag || Set when interrupts are enabled, cleared on disable
|-
| IFF2 || 1-bit || Backup of IFF1 during NMIs || Restores IFF1 after returning from an NMI
|-
| WZ || 16-bit || Internal temporary register pair || Used for memory and address calculations (not user-accessible)
|}
== Opcodes ==
